On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
> ACPI ISA strings are based on a specification after Zicsr and Zifencei
> were split out of I, so we shouldn't be treating them as part of I. We
> haven't release an ACPI-based kernel yet, so we don't need to worry
> about compatibility with the old ISA strings.
>
> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
> Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
> ---
LGTM. I agree with Conor that Fixes tag should point to 07edc32779e3.
Reviewed-by: Sunil V L <sunilvl@xxxxxxxxxxxxxxxx>
Thanks,
Sunil
> arch/riscv/kernel/cpufeature.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index bdcf460ea53d..a8f66c015229 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
> #undef SET_ISA_EXT_MAP
> }
>
> - /*
> - * Linux requires the following extensions, so we may as well
> - * always set them.
> - */
> - set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> - set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> -
> /*
> * These ones were as they were part of the base ISA when the
> * port & dt-bindings were upstreamed, and so can be set
> * unconditionally where `i` is in riscv,isa on DT systems.
> */
> if (acpi_disabled) {
> + set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> + set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
> }
> --
> 2.40.1
>
