On Mon, Jun 12, 2023 at 03:32:42PM -0700, Dave Jiang wrote: > Dan Williams suggested changing the struct 'node_hmem_attrs' to > 'access_coordinates' [1]. The struct is a container of r/w-latency and > r/w-bandwidth numbers. Moving forward, this container will also be used by > CXL to store the performance characteristics of each link hop in > the PCIE/CXL topology. So, where node_hmem_attrs is just the access > parameters of a memory-node, access_coordinates applies more broadly > to hardware topology characteristics. The observation is that seemed like > an excercise in having the application identify "where" it falls on a > spectrum of bandwidth and latency needs. For the tuple of read/write-latency > and read/write-bandwidth, "coordinates" is not a perfect fit. Sometimes it > is just conveying values in isolation and not a "location" relative to > other performance points, but in the end this data is used to identify the > performance operation point of a given memory-node. [2] > > Link: http://lore.kernel.org/r/64471313421f7_1b66294d5@xxxxxxxxxxxxxxxxxxxxxxxxx.notmuch/ > Link: https://lore.kernel.org/linux-cxl/645e6215ee0de_1e6f2945e@xxxxxxxxxxxxxxxxxxxxxxxxx.notmuch/ > Suggested-by: Dan Williams <dan.j.williams@xxxxxxxxx> > Reviewed-by: Dan Williams <dan.j.williams@xxxxxxxxx> > Signed-off-by: Dave Jiang <dave.jiang@xxxxxxxxx> > > --- > > Hi Greg and Rafael, > please consider ACK this patch and Dan can take it through the > CXL upstream tree. The remaining ACPI [1] and CXL [2] patches for enabling > CXL QoS class data have dependency on this patch. Thank you! > > [1]: https://lore.kernel.org/linux-cxl/168333141100.2290593.16294670316057617744.stgit@djiang5-mobl3/T/#t > [2]: https://lore.kernel.org/linux-cxl/168451588868.3470703.3527256859632103687.stgit@djiang5-mobl3/T/#t Acked-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
