On Wed, Mar 22, 2023 at 07:57:19PM +0100, Andrew Lunn wrote:
> > +static struct fwnode_handle *mv88e6xxx_port_get_fwnode(struct dsa_switch *ds,
> > + int port,
> > + struct fwnode_handle *h)
> > +{
> > + struct mv88e6xxx_chip *chip = ds->priv;
> > + struct device_node *np, *phy_node;
> > + int speed, duplex, err;
> > + phy_interface_t mode;
> > + struct dsa_port *dp;
> > + unsigned long caps;
> > +
> > + dp = dsa_to_port(ds, port);
> > + if (dsa_port_is_user(dp))
> > + return h;
> > +
> > + /* No DT? Eh? */
> > + np = to_of_node(h);
> > + if (!np)
> > + return h;
>
> I've not looked at the big picture yet, but you can have a simple
> switch setup without DT. I have a couple of amd64 boards which use
> platform data. The user ports all have internal PHYs, and the CPU port
> defaults to 1G, it might even be strapped that way.
Are you suggesting that we should generate some swnode description of
the max interface mode and speed if we are missing a DT node?
I'm not seeing any port specific data in the mv88e6xxx platform data.
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