On Thu, Feb 16, 2023 at 11:50:39PM +0530, Sunil V L wrote:
> On ACPI based platforms, timer related information is
> available in RHCT. Add ACPI based probe support to the
> timer initialization.
>
> Signed-off-by: Sunil V L <sunilvl@xxxxxxxxxxxxxxxx>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
> ---
> arch/riscv/kernel/time.c | 25 +++++++++++++++++++------
> 1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
> index 1cf21db4fcc7..e49b897fc657 100644
> --- a/arch/riscv/kernel/time.c
> +++ b/arch/riscv/kernel/time.c
> @@ -4,6 +4,7 @@
> * Copyright (C) 2017 SiFive
> */
>
> +#include <linux/acpi.h>
> #include <linux/of_clk.h>
> #include <linux/clockchips.h>
> #include <linux/clocksource.h>
> @@ -18,17 +19,29 @@ EXPORT_SYMBOL_GPL(riscv_timebase);
> void __init time_init(void)
> {
> struct device_node *cpu;
> + struct acpi_table_rhct *rhct;
> + acpi_status status;
> u32 prop;
>
> - cpu = of_find_node_by_path("/cpus");
> - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
> - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
> - of_node_put(cpu);
> - riscv_timebase = prop;
> + if (acpi_disabled) {
> + cpu = of_find_node_by_path("/cpus");
> + if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
> + panic("RISC-V system with no 'timebase-frequency' in DTS\n");
> + of_node_put(cpu);
> + riscv_timebase = prop;
> + } else {
> + status = acpi_get_table(ACPI_SIG_RHCT, 0, (struct acpi_table_header **)&rhct);
> + if (ACPI_FAILURE(status))
> + panic("RISC-V ACPI system with no RHCT table\n");
> + riscv_timebase = rhct->time_base_freq;
> + acpi_put_table((struct acpi_table_header *)rhct);
> + }
>
> lpj_fine = riscv_timebase / HZ;
>
> - of_clk_init(NULL);
> + if (acpi_disabled)
> + of_clk_init(NULL);
I think we should be able to move of_clk_init() up into the acpi_disabled
arm rather than add another if here.
> +
> timer_probe();
>
> tick_setup_hrtimer_broadcast();
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
