On Mon, Jan 30, 2023 at 7:22 PM Sunil V L <sunilvl@xxxxxxxxxxxxxxxx> wrote: > > This patch series enables the basic ACPI infrastructure for RISC-V. > Supporting external interrupt controllers is in progress and hence it is > tested using polling based HVC SBI console and RAM disk. > > The series depends on Anup's IPI improvement series. > https://github.com/avpatel/linux/commits/riscv_ipi_imp_v17 > > These changes are available at > https://github.com/vlsunil/linux/commits/acpi_b1_us_review_ipi17 > > Testing: > 1) Build Qemu with ACPI support using below branch > https://github.com/vlsunil/qemu/tree/acpi_b1_us_review > > 2) Build EDK2 as per instructions in > https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support > > 3) Build Linux after enabling SBI HVC and SBI earlycon > CONFIG_RISCV_SBI_V01=y > CONFIG_SERIAL_EARLYCON_RISCV_SBI=y > CONFIG_HVC_RISCV_SBI=y > > 4) Build buildroot. > > Run with below command. > qemu-system-riscv64 -nographic \ > -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \ > -machine virt,acpi=on -smp 16 -m 2G \ > -kernel arch/riscv/boot/Image \ > -initrd buildroot/output/images/rootfs.cpio \ > -append "root=/dev/ram ro console=hvc0 earlycon=sbi" > > Jisheng Zhang (1): > riscv: move sbi_init() earlier before jump_label_init() > > Sunil V L (23): > ACPICA: MADT: Add RISC-V INTC interrupt controller > ACPICA: Add structure definitions for RISC-V RHCT > RISC-V: ACPI: Add empty headers to enable ACPI core > RISC-V: ACPI: Add basic functions to build ACPI core > RISC-V: ACPI: Add PCI functions to build ACPI core > RISC-V: ACPI: Enable ACPI build infrastructure > ACPI: Enable ACPI_PROCESSOR for RISC-V > ACPI: OSL: Make should_use_kmap() 0 for RISC-V. > ACPI: processor_core: RISC-V: Enable mapping processor to the hartid > RISC-V: ACPI: irqchip/riscv-intc: Add ACPI support > RISC-V: ACPI: smpboot: Create wrapper smp_setup() > RISC-V: ACPI: smpboot: Add ACPI support in smp_setup() > RISC-V: ACPI: smpboot: Add function to retrieve the hartid > clocksource/timer-riscv: Refactor riscv_timer_init_dt() > RISC-V: ACPI: clocksource/timer-riscv: Add ACPI support > ACPI: RISC-V: drivers/acpi: Add RHCT related code > RISC-V: ACPI: time.c: Add ACPI support for time_init() > RISC-V: ACPI: cpufeature: Add ACPI support in riscv_fill_hwcap() > RISC-V: ACPI: cpu: Enable cpuinfo for ACPI systems > RISC-V: ACPI: Add ACPI initialization in setup_arch() > RISC-V: ACPI: Enable ACPI in defconfig > MAINTAINERS: Add entry for drivers/acpi/riscv > Documentation/kernel-parameters.txt: Add RISC-V for ACPI parameter The series looks fine to me from the ACPI perspective, so please feel free to add Acked-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx> to it and route it via RISC-V. Thanks!
