On Fri, Oct 21, 2022 at 11:09:27AM +0200, Linus Walleij wrote: > On Wed, Oct 19, 2022 at 4:26 AM chengwei <foxfly.lai.tw@xxxxxxxxx> wrote: > > The UP Squared board <http://www.upboard.com> implements certain > > features (pin control) through an on-board FPGA. > I am a bit confused by this driver. Andy pointed out some obvious nits that > need to be fixed but the overall architecture here is also a bit puzzling. > > This seems to want to be compatible to Raspberry Pi (RPi), then which one? > > The driver seems to translate GPIO calls to "native GPIO" in some cases, > which GPIO controller is that? There is an SoC level GPIO (Apollo Lake I believe) and there is a discrete component between it and user visible header (connector). This driver AFAIU is about controlling that discrete component. > Also I don't see why, normally a pin control > driver is an agnostic back-end for a GPIO controller, so the GPIO driver > should be the same (whatever "native") means, and this driver should > not even implement a gpio chip, just let the GPIO driver do its job > and call back into the pin control back-end whenever it needs it. > > Also we already have a driver that collects existing GPIOs to a new > GPIO chip, the GPIO aggregator: > drivers/gpio/gpio-aggregator.c > > Maybe if you can explain a bit about how this hardware works and why > you have to do indirect calls to another GPIO controller, things will > be easier to understand? -- With Best Regards, Andy Shevchenko
