LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its boot protocol LoongArch-specific interrupt controllers (similar to APIC) are already added in the next revision of ACPI Specification (current revision is 6.4). This patchset are preparing to add LoongArch support in mainline kernel, we can see a snapshot here: https://github.com/loongson/linux/tree/loongarch-next Cross-compile tool chain to build kernel: https://github.com/loongson/build-tools/releases Loongson and LoongArch documentations: https://github.com/loongson/LoongArch-Documentation ECR for LoongArch-specific interrupt controllers: https://mantis.uefi.org/mantis/view.php?id=2203 https://mantis.uefi.org/mantis/view.php?id=2313 ACPI changes of LoongArch have been approved in the last year, but the new version of ACPI SPEC hasn't been made public yet. V2: Remove merged patches and update commit messages. Huacai Chen and Jianmin Lv(2): ACPICA: MADT: Add LoongArch APICs support. ACPICA: Events: Support fixed pcie wake event. Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx> Signed-off-by: Jianmin Lv <lvjianmin@xxxxxxxxxxx> --- drivers/acpi/acpica/evevent.c | 17 ++++-- drivers/acpi/acpica/hwsleep.c | 12 ++++ drivers/acpi/acpica/utglobal.c | 4 ++ drivers/acpi/tables.c | 10 ++++ include/acpi/actbl2.h | 125 ++++++++++++++++++++++++++++++++++++++++- include/acpi/actypes.h | 3 +- 6 files changed, 163 insertions(+), 8 deletions(-) -- 2.27.0
