On 12/3/21 3:49 PM, Kirill A. Shutemov wrote: > - ACPI_FLUSH_CPU_CACHE(); > + if (acpi_state >= ACPI_STATE_S1 && acpi_state <= ACPI_STATE_S3) > + ACPI_FLUSH_CPU_CACHE(); It's a bit of a bummer that this per-sleep-state logic has to be repeated so many time. If you pass acpi_state into ACPI_FLUSH_CPU_CACHE() can you centralize the set of places where that knowledge about which sleep states require flushing? > TDX doesn't support these S- and C-states. TDX is only supports S0 and S5. This makes me a bit nervous. Is this "the first TDX implementation supports..." or "the TDX architecture *prohibits* supporting S1 (or whatever"? I really think we need some kind of architecture guarantee. Without that, we risk breaking things if someone at our employer simply changes their mind. The: > #define ACPI_FLUSH_CPU_CACHE_PHYS() \ > if (!cpu_feature_enabled(XXX)) \ > wbinvd(); \ does seem simpler and less error-prone than this, though.
