Re: [PATCH v2 2/2] ACPI / PMIC: XPower: optimize MIPI PMIQ sequence I2C-bus accesses

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On Tue, Jul 06, 2021 at 08:27:55PM +0200, Hans de Goede wrote:
> On 7/6/21 6:35 PM, Andy Shevchenko wrote:
> > On Tue, Jul 06, 2021 at 06:09:23PM +0200, Hans de Goede wrote:

...

> > The idea for the further improvement
> > 
> >> +	if (i2c_address != 0x34) {
> >> +		pr_err("%s: Unexpected i2c-addr: 0x%02x (reg-addr 0x%x value 0x%x mask 0x%x)\n",
> >> +		       __func__, i2c_address, reg_address, value, mask);
> >> +		return -ENXIO;
> >> +	}
> > 
> > We have this in intel_pmic.c. Can we reorganize the code the way we will have
> > this check solely in the intel_pmic.c?
> 
> No, the drivers/acpi/pmic/intel_pmic_chtwc.c implementation accepts multiple
> i2c addresses because the whiskey cove has multiple register banks split
> over different i2c-addressses.

I think it's still possible (by modifying the field to be an array of accepted
addresses). Anyway, it's matter outside of this patch series and we have time
to think about it.

-- 
With Best Regards,
Andy Shevchenko





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