The Microsoft Surface Pro X has host bridges defined as
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0x60200000, // Address Base
0x01DF0000, // Address Length
)
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x0001, // Range Maximum
0x0000, // Translation Offset
0x0002, // Length
,, )
})
Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
}
meaning that the memory resources aren't (explicitly) defined as
"producers", i.e. host bridge windows.
Commit 8fd4391ee717 ("arm64: PCI: Exclude ACPI "consumer" resources from
host bridge windows") introduced a check that removes such resources,
causing BAR allocation failures later on:
[ 0.150731] pci 0002:00:00.0: BAR 14: no space for [mem size 0x00100000]
[ 0.150744] pci 0002:00:00.0: BAR 14: failed to assign [mem size 0x00100000]
[ 0.150758] pci 0002:01:00.0: BAR 0: no space for [mem size 0x00004000 64bit]
[ 0.150769] pci 0002:01:00.0: BAR 0: failed to assign [mem size 0x00004000 64bit]
This eventually prevents the PCIe NVME drive from being accessible.
On x86 we already skip the check for producer/window due to some history
with negligent firmware. It seems that Microsoft is intent on continuing
that history on their ARM devices, so let's drop that check here too.
Signed-off-by: Maximilian Luz <luzmaximilian@xxxxxxxxx>
---
Please note: I am not sure if this is the right way to fix that, e.g. I
don't know if any additional checks like on IA64 or x86 might be
required instead, or if this might break things on other devices. So
please consider this more as a bug report rather than a fix.
Apologies for the re-send, I seem to have unintentionally added a blank
line before the subject.
---
arch/arm64/kernel/pci.c | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index 1006ed2d7c60..80f87fe0a2b8 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -94,19 +94,6 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
return 0;
}
-static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
-{
- struct resource_entry *entry, *tmp;
- int status;
-
- status = acpi_pci_probe_root_resources(ci);
- resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
- if (!(entry->res->flags & IORESOURCE_WINDOW))
- resource_list_destroy_entry(entry);
- }
- return status;
-}
-
/*
* Lookup the bus range for the domain in MCFG, and set up config space
* mapping.
@@ -184,7 +171,6 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
}
root_ops->release_info = pci_acpi_generic_release_info;
- root_ops->prepare_resources = pci_acpi_root_prepare_resources;
root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops;
bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg);
if (!bus)
--
2.31.1
