On Fri, 7 May 2021 15:51:31 -0700
Dan Williams <dan.j.williams@xxxxxxxxx> wrote:
> In preparation for more generic shared functionality across endpoint
> consumers of core cxl resources, and platform-firmware producers of
> those resources, rename bus.c to core.c. In addition to the central
> rendezvous for interleave coordination, the core will also define common
> routines like CXL register block mapping.
>
> Acked-by: Ben Widawsky <ben.widawsky@xxxxxxxxx>
> Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> ---
> Documentation/driver-api/cxl/memory-devices.rst | 6 ++---
> drivers/cxl/Makefile | 4 ++-
> drivers/cxl/bus.c | 29 ----------------------
> drivers/cxl/core.c | 30 +++++++++++++++++++++++
> 4 files changed, 35 insertions(+), 34 deletions(-)
> delete mode 100644 drivers/cxl/bus.c
> create mode 100644 drivers/cxl/core.c
>
> diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
> index 1bad466f9167..71495ed77069 100644
> --- a/Documentation/driver-api/cxl/memory-devices.rst
> +++ b/Documentation/driver-api/cxl/memory-devices.rst
> @@ -28,10 +28,10 @@ CXL Memory Device
> .. kernel-doc:: drivers/cxl/mem.c
> :internal:
>
> -CXL Bus
> +CXL Core
> -------
> -.. kernel-doc:: drivers/cxl/bus.c
> - :doc: cxl bus
> +.. kernel-doc:: drivers/cxl/core.c
> + :doc: cxl core
>
> External Interfaces
> ===================
> diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
> index a314a1891f4d..3808e39dd31f 100644
> --- a/drivers/cxl/Makefile
> +++ b/drivers/cxl/Makefile
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_CXL_BUS) += cxl_bus.o
> +obj-$(CONFIG_CXL_BUS) += cxl_core.o
> obj-$(CONFIG_CXL_MEM) += cxl_mem.o
>
> ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL
> -cxl_bus-y := bus.o
> +cxl_core-y := core.o
> cxl_mem-y := mem.o
> diff --git a/drivers/cxl/bus.c b/drivers/cxl/bus.c
> deleted file mode 100644
> index 58f74796d525..000000000000
> --- a/drivers/cxl/bus.c
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
> -#include <linux/device.h>
> -#include <linux/module.h>
> -
> -/**
> - * DOC: cxl bus
> - *
> - * The CXL bus provides namespace for control devices and a rendezvous
> - * point for cross-device interleave coordination.
> - */
> -struct bus_type cxl_bus_type = {
> - .name = "cxl",
> -};
> -EXPORT_SYMBOL_GPL(cxl_bus_type);
> -
> -static __init int cxl_bus_init(void)
> -{
> - return bus_register(&cxl_bus_type);
> -}
> -
> -static void cxl_bus_exit(void)
> -{
> - bus_unregister(&cxl_bus_type);
> -}
> -
> -module_init(cxl_bus_init);
> -module_exit(cxl_bus_exit);
> -MODULE_LICENSE("GPL v2");
> diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
> new file mode 100644
> index 000000000000..7f8d2034038a
> --- /dev/null
> +++ b/drivers/cxl/core.c
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
> +#include <linux/device.h>
> +#include <linux/module.h>
> +
> +/**
> + * DOC: cxl core
> + *
> + * The CXL core provides a sysfs hierarchy for control devices and a rendezvous
> + * point for cross-device interleave coordination through cxl ports.
> + */
> +
> +struct bus_type cxl_bus_type = {
> + .name = "cxl",
> +};
> +EXPORT_SYMBOL_GPL(cxl_bus_type);
> +
> +static __init int cxl_core_init(void)
> +{
> + return bus_register(&cxl_bus_type);
> +}
> +
> +static void cxl_core_exit(void)
> +{
> + bus_unregister(&cxl_bus_type);
> +}
> +
> +module_init(cxl_core_init);
> +module_exit(cxl_core_exit);
> +MODULE_LICENSE("GPL v2");
>
