On 2019/8/21 下午5:17, Greg Kroah-Hartman wrote:
On Wed, Aug 21, 2019 at 03:21:18PM +0800, zhangfei.gao@xxxxxxxxxxx wrote:
Hi, Greg
On 2019/8/21 上午12:59, Greg Kroah-Hartman wrote:
On Tue, Aug 20, 2019 at 09:08:55PM +0800, zhangfei wrote:
On 2019/8/15 下午10:13, Greg Kroah-Hartman wrote:
On Wed, Aug 14, 2019 at 05:34:25PM +0800, Zhangfei Gao wrote:
+int uacce_register(struct uacce *uacce)
+{
+ int ret;
+
+ if (!uacce->pdev) {
+ pr_debug("uacce parent device not set\n");
+ return -ENODEV;
+ }
+
+ if (uacce->flags & UACCE_DEV_NOIOMMU) {
+ add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
+ dev_warn(uacce->pdev,
+ "Register to noiommu mode, which export kernel data to user space and may vulnerable to attack");
+ }
THat is odd, why even offer this feature then if it is a major issue?
UACCE_DEV_NOIOMMU maybe confusing here.
In this mode, app use ioctl to get dma_handle from dma_alloc_coherent.
That's odd, why not use the other default apis to do that?
It does not matter iommu is enabled or not.
In case iommu is disabled, it maybe dangerous to kernel, so we added warning here, is it required?
You should use the other documentated apis for this, don't create your
own.
I am sorry, not understand here.
Do you mean there is a standard ioctl or standard api in user space, it can
get dma_handle from dma_alloc_coherent from kernel?
There should be a standard way to get such a handle from userspace
today. Isn't that what the ion interface does? DRM also does this, as
does UIO I think.
Thanks Greg,
Still not find it, will do more search.
But this may introduce dependency in our lib, like depend on ion?
Do you have a spec somewhere that shows exactly what you are trying to
do here, along with example userspace code? It's hard to determine it
given you only have one "half" of the code here and no users of the apis
you are creating.
The purpose is doing dma in user space.
If sva is supported, we can directly use malloc memory.
If sva is not supported, device can not recognize va, so we get
dma_handle via ioctl.
Sample user code is in
https://github.com/Linaro/warpdrive/blob/wdprd-v1-current/test/test_hisi_zip.c
hizip_wd_sched_init_cache:
if (sched->qs[0].dev_flags & UACCE_DEV_NOIOMMU) {
data_in = wd_get_pa_from_va(&sched->qs[0], wd_msg->data_in);
data_out = wd_get_pa_from_va(&sched->qs[0], wd_msg->data_out);
} else {
data_in = wd_msg->data_in;
data_out = wd_msg->data_out;
}
msg->source_addr_l = (__u64)data_in & 0xffffffff;
msg->source_addr_h = (__u64)data_in >> 32;
msg->dest_addr_l = (__u64)data_out & 0xffffffff;
msg->dest_addr_h = (__u64)data_out >> 32;
Have added some explanation in warpdrive.rst, in the first patch.
The device can also be declared as UACCE_DEV_NOIOMMU. It can be used
when the
device has no iommu support or the iommu is set in pass through mode.
In this
case, the driver should map address to device by itself with DMA API. The
ioctl(UACCE_CMD_GET_SS_DMA) can be used to get the physical address,
though it
is an untrusted and kernel-tainted behavior.
Thanks
