On 12/12/13 11:36, Peter Maydell wrote: > On 12 December 2013 09:32, Andre Przywara <andre.przywara@xxxxxxxxxx> wrote: >> On 12/12/2013 10:23 AM, Peter Maydell wrote: >>> What does it mean to say that a system register for AArch64 >>> is "32 bits" given that MRS/MSR always operate on a 64 bit >>> register? > >> But ARMv8 ARM still defines these registers as 32-bit: >> D8.5.14: CNTV_CTL_EL0 >> Attributes >> CNTV_CTL_EL0 is a 32-bit register. >> But indeed the MSR/MRS instruction references a Xt register, and the >> documentation does not seem to tell how this is handled, so I assume this is >> zero-extended. > > I checked, and for AArch64 registers, "32 bits" is just > a shorthand for "64 bit register where the top 32 bits are > RAZ/WI" (and I suspect it's not totally impossible that some > future architecture revision might define new bits in the > top half). Indeed. Actually, there isn't an instruction to access these 32bit registers with a 'W' register. You really have to use a 'X'. > So I would suggest that we should make the KVM user<->kernel > interface just consistently make all the sysregs 64 bit. > > (There is actually precedent of a sort here in that the > kernel claims the PSTATE register is 64 bits wide despite > it really being a 32 bit SPSR format value under the hood.) I definitely agree with Peter here. I'd like to keep the ABI 64bit for the sysregs. It makes the whole thing much nicer. Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
