On 05.09.2013, at 22:22, Paul Mackerras wrote: > POWER7 and later IBM server processors have a register called the > Program Priority Register (PPR), which controls the priority of > each hardware CPU SMT thread, and affects how fast it runs compared > to other SMT threads. This priority can be controlled by writing to > the PPR or by use of a set of instructions of the form or rN,rN,rN > which are otherwise no-ops but have been defined to set the priority > to particular levels. > > This adds code to context switch the PPR when entering and exiting > guests and to make the PPR value accessible through the SET/GET_ONE_REG > interface. When entering the guest, we set the PPR as late as > possible, because if we are setting a low thread priority it will > make the code run slowly from that point on. Similarly, the > first-level interrupt handlers save the PPR value in the PACA very > early on, and set the thread priority to the medium level, so that > the interrupt handling code runs at a reasonable speed. > > Signed-off-by: Paul Mackerras <paulus@xxxxxxxxx> Reviewed-by: Alexander Graf <agraf@xxxxxxx> Alex -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
