> -----Original Message----- > From: kvm-ppc-owner@xxxxxxxxxxxxxxx [mailto:kvm-ppc-owner@xxxxxxxxxxxxxxx] On > Behalf Of Alexander Graf > Sent: Friday, July 26, 2013 2:20 PM > To: Benjamin Herrenschmidt > Cc: Bhushan Bharat-R65777; kvm-ppc@xxxxxxxxxxxxxxx; kvm@xxxxxxxxxxxxxxx; > linuxppc-dev@xxxxxxxxxxxxxxxx; Wood Scott-B07421; Bhushan Bharat-R65777 > Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages > > > On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote: > > > On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote: > >> If the page is RAM then map this as cacheable and coherent (set "M" > >> bit) otherwise this page is treated as I/O and map this as cache > >> inhibited and guarded (set "I + G") > >> > >> This helps setting proper MMU mapping for direct assigned device. > >> > >> NOTE: There can be devices that require cacheable mapping, which is not yet > supported. > > > > Why don't you do like server instead and enforce the use of the same I > > and M bits as the corresponding qemu PTE ? > > Specifically, Ben is talking about this code: > > > /* Translate to host virtual address */ > hva = __gfn_to_hva_memslot(memslot, gfn); > > /* Look up the Linux PTE for the backing page */ > pte_size = psize; > pte = lookup_linux_pte(pgdir, hva, writing, &pte_size); > if (pte_present(pte)) { > if (writing && !pte_write(pte)) > /* make the actual HPTE be read-only */ > ptel = hpte_make_readonly(ptel); > is_io = hpte_cache_bits(pte_val(pte)); > pa = pte_pfn(pte) << PAGE_SHIFT; > } > Ok Thanks -Bharat > > Alex > > -- > To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body > of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at > http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
