Intercepting task switches in svm/vmx with tdp enabled

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Hi,

I am interested in intercepting task switches in vmx/svm in 64 bit
mode with ept/npt enabled.
However, I am not seeing the exit code due to task switch ( 9 for vmx
and 125 for svm ) in the list of vm exits that I see in a typical
guest run.
I log the vm exit codes in the x86/svm.c:handle_exit method for svm
and x86/vmx.c:vmx_handle_exit for vmx.

Any pointers regarding this is very much appreciated.

On a related note, does cr3 write interception approximate task switch
interception ?
( I was able to intercept cr3 writes with svm while npt was enabled.
but with vmx, I could intercept cr3 writes only with ept disabled )

Thanks,
Leo

Looking through the manuals, svm has a control bit in VMCS for
enabling / disabling task switch interception while vmx does not seem
to have such a control bit.
-----------------------------------------
Excerpts from the manuals :

Intel
------

Exit reason #9 indicates a vm exit due to task switch.

Vol. 3C 24-9 : Some instructions cause VM exits regardless of the
settings of the processor-based VM-execution controls (see Section
25.1.2), as
do task switches (see Section 25.2).

Vol. 3C 25-6 : Task switches. Task switches are not allowed in VMX
non-root operation. Any attempt to effect a task switch in VMX
non-root operation causes a VM exit. See Section 25.4.2

AMD
-------

Intercept code to look for is: 7Dh VMEXIT_TASK_SWITCH task switch

15.14 AMD64 Technology Miscellaneous Intercepts : The SVM architecture
includes intercepts to handle task switches, processor freezes due to
FERR, and shutdown operations.
Task switches can modify several resources that a VMM may want to
protect (CR3, EFLAGS, LDT).  However, instead of checking various
intercepts (e.g., CR3 Write, LDTR Write) individually, task switches
check only a single intercept bit.

Page 581 : Layout of VMCB says Byte offset 00Ch : bit 29 Intercept
task switches.

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