On Wed, May 29, 2013 at 09:55:55AM -0500, Anthony Liguori wrote: > > Not we. The BIOS can disable IO BAR: it can do this already > > but the device won't be functional. > > But the only way to expose the device over PCI express is to disable the > IO BAR, right? I think this is the source of the misunderstanding: 1.3.2.2. PCI Express Endpoint Rules ... PCI Express Endpoint must not depend on operating system allocation of I/O resources claimed through BAR(s). The real meaning here is *not* that an Endpoint should not have an I/O BAR. An Endpoint can have an I/O BAR, and PCI Express spec supports I/O transactions. The meaning is that an Endpoint should work even if *the OS* decides to disable the I/O BAR. Note: it's up to the guest. We support I/O as a device with full compatibility for old guests, but must be prepared to handle a guest which does not enable I/O. This likely means that as time goes on, future OSes will start disabling I/O BARs, relying on this not hurting functionality. -- MST -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
