Il 19/05/2013 07:47, Sanjay Lal ha scritto:
> +static int kvm_vz_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
> +{
> + struct mips_coproc *cop0 = vcpu->arch.cop0;
> +
> + /* some registers are not restored
> + * random, count : read-only
> + * userlocal : not implemented in qemu
> + * config6 : not implemented in processor variant
> + * compare, cause : defer to kvm_vz_restore_guest_timer_int
> + */
> +
> + kvm_write_c0_guest_index(cop0, regs->cp0reg[MIPS_CP0_TLB_INDEX][0]);
> + kvm_write_c0_guest_entrylo0(cop0, regs->cp0reg[MIPS_CP0_TLB_LO0][0]);
> + kvm_write_c0_guest_entrylo1(cop0, regs->cp0reg[MIPS_CP0_TLB_LO1][0]);
> + kvm_write_c0_guest_context(cop0, regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0]);
> + kvm_write_c0_guest_pagemask(cop0,
> + regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0]);
> + kvm_write_c0_guest_pagegrain(cop0,
> + regs->cp0reg[MIPS_CP0_TLB_PG_MASK][1]);
> + kvm_write_c0_guest_wired(cop0, regs->cp0reg[MIPS_CP0_TLB_WIRED][0]);
> + kvm_write_c0_guest_hwrena(cop0, regs->cp0reg[MIPS_CP0_HWRENA][0]);
> + kvm_write_c0_guest_badvaddr(cop0, regs->cp0reg[MIPS_CP0_BAD_VADDR][0]);
> + /* skip kvm_write_c0_guest_count */
> + kvm_write_c0_guest_entryhi(cop0, regs->cp0reg[MIPS_CP0_TLB_HI][0]);
> + /* defer kvm_write_c0_guest_compare */
> + kvm_write_c0_guest_status(cop0, regs->cp0reg[MIPS_CP0_STATUS][0]);
> + kvm_write_c0_guest_intctl(cop0, regs->cp0reg[MIPS_CP0_STATUS][1]);
> + /* defer kvm_write_c0_guest_cause */
> + kvm_write_c0_guest_epc(cop0, regs->cp0reg[MIPS_CP0_EXC_PC][0]);
> + kvm_write_c0_guest_prid(cop0, regs->cp0reg[MIPS_CP0_PRID][0]);
> + kvm_write_c0_guest_ebase(cop0, regs->cp0reg[MIPS_CP0_PRID][1]);
> +
> + /* only restore implemented config registers */
> + kvm_write_c0_guest_config(cop0, regs->cp0reg[MIPS_CP0_CONFIG][0]);
> +
> + if ((regs->cp0reg[MIPS_CP0_CONFIG][0] & MIPS_CONF_M) &
> + cpu_vz_has_config1)
> + kvm_write_c0_guest_config1(cop0,
> + regs->cp0reg[MIPS_CP0_CONFIG][1]);
> +
> + if ((regs->cp0reg[MIPS_CP0_CONFIG][1] & MIPS_CONF_M) &
> + cpu_vz_has_config2)
> + kvm_write_c0_guest_config2(cop0,
> + regs->cp0reg[MIPS_CP0_CONFIG][2]);
> +
> + if ((regs->cp0reg[MIPS_CP0_CONFIG][2] & MIPS_CONF_M) &
> + cpu_vz_has_config3)
> + kvm_write_c0_guest_config3(cop0,
> + regs->cp0reg[MIPS_CP0_CONFIG][3]);
> +
> + if ((regs->cp0reg[MIPS_CP0_CONFIG][3] & MIPS_CONF_M) &
> + cpu_vz_has_config4)
> + kvm_write_c0_guest_config4(cop0,
> + regs->cp0reg[MIPS_CP0_CONFIG][4]);
> +
> + if ((regs->cp0reg[MIPS_CP0_CONFIG][4] & MIPS_CONF_M) &
> + cpu_vz_has_config5)
> + kvm_write_c0_guest_config5(cop0,
> + regs->cp0reg[MIPS_CP0_CONFIG][5]);
> +
> + if (cpu_vz_has_config6)
> + kvm_write_c0_guest_config6(cop0,
> + regs->cp0reg[MIPS_CP0_CONFIG][6]);
> + if (cpu_vz_has_config7)
> + kvm_write_c0_guest_config7(cop0,
> + regs->cp0reg[MIPS_CP0_CONFIG][7]);
> +
> + kvm_write_c0_guest_errorepc(cop0, regs->cp0reg[MIPS_CP0_ERROR_PC][0]);
> +
> + /* call after setting MIPS_CP0_CAUSE to avoid having it overwritten
> + * this will set guest compare and cause.TI if necessary
> + */
> + kvm_vz_restore_guest_timer_int(vcpu, regs);
> +
> + return 0;
> +}
All this is now obsolete after David's patches (reusing kvm_regs looked
a bit strange in fact).
Paolo
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