Hi Marc,
On 03/12/2013 02:05 PM, Marc Zyngier wrote:
> On 12/03/13 17:31, Christopher Covington wrote:
>> Hi Marc,
>>
>> On 03/04/2013 10:47 PM, Marc Zyngier wrote:
>>> Let userspace play with the guest registers.
>>>
>>> Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
>>> ---
>>> arch/arm64/kvm/guest.c | 240 +++++++++++++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 240 insertions(+)
>>> create mode 100644 arch/arm64/kvm/guest.c
>>
>> [...]
>>
>>> +int __attribute_const__ kvm_target_cpu(void)
>>> +{
>>> + unsigned long implementor = read_cpuid_implementor();
>>> + unsigned long part_number = read_cpuid_part_number();
>>> +
>>> + if (implementor != ARM_CPU_IMP_ARM)
>>> + return -EINVAL;
>>> +
>>> + switch (part_number) {
>>> + case ARM_CPU_PART_AEM_V8:
>>> + case ARM_CPU_PART_FOUNDATION:
>>> + /* Treat the models just as an A57 for the time being */
>>> + case ARM_CPU_PART_CORTEX_A57:
>>> + return KVM_ARM_TARGET_CORTEX_A57;
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>
>> What is the motivation behind these checks? Why not let any ARMv8 system that
>> has EL2 host a virtualized Cortex A57 guest?
>
> The main reason is errata management. How do you deal with errata in the
> guest when you hide the underlying host CPU? I don't have an answer to
> that. So for the time being, we only allow the guest to see the same CPU
> as the host, and require that new CPUs are added to this function.
Can you please elaborate on how this code ensures the guest is seeing the same
CPU as the host? It looks rather unlike VPIDR = MIDR.
Thanks,
Christopher
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