On Wed, Mar 06, 2013 at 03:48:54PM +0100, Alexander Graf wrote: > > Paul, Scott, do you think we can move the "this CPU can receive > interrupts from MPIC / XICS" part into an ENABLE_CAP that gets set > dynamically? That ENABLE_CAP would allocate the structures in the vcpu > and register the vcpu with the interrupt controller pool. > > The interrupt controller device would still iterate through all > vcpus to find the ones that match so that we support the ENABLE_CAP at > any point in time. When you say "gets set dynamically", do you mean some time in the interval between vcpu creation and when it starts running, or do you mean at any time, potentially after the vcpu has accessed and modified its per-vcpu interrupt controller (~ LAPIC) state? If the former, then sure, I don't see a major problem. If the latter, then we'd have to atomically transfer the "LAPIC" state from userspace to the kernel at the same time as we did the ENABLE_CAP - which is certainly possible, but we'd need the vcpu to be not running at the time. Paul. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
