Hello lists, As a QEMU developper I am looking for a way to help improving qemu/kvm block performance for $customer. Having read about APIC-V on #qemu I looked at the intel manual in order to have an idea of what is an APIC and what is APIC-V. Here is a summary that I am posting so it can help people like me with the acronyms. Feel free to correct me if I am saying something incorrect or incomplete or just ignore the post if it's too trivial. >From Intel manual volume 3A chapter 6 "interruptions": ------------------------------------------------------ There are 256 interruptions possible on an x86 system and the first 32 are reserved. The IDT (interrupt descriptor table) is indexed by the interruption vector and it's size can be at most 256. >From Intel manual volume 3A chapter 10 "APIC": ---------------------------------------------- The local APIC (Advanced Programable Interrupt Controller)'s job is to forward local interrupts (timer, thermal events) or external interrupts (IO-APIC on the PCI bus for example) to the CPU. When the APIC does this the cpu program counter jump to the routine located at IDT[vector]. When an interrupt routine is ending and EIO (End Of Interrupt) can be written is a dedicated register of the local APIC to inform it that the interrupt has been processed. The local APIC can propagate EIOs automatically. EIOs can also be sent directly at the I/O APIC located on the PCI bus to avoid the need of propagation. The configuration of the local APIC is in most case done on a 4KB region which address is configurable in the IA32_APIC_BASE register. An IPI (Inter Processor Interrupt) can be send by a local APIC after a serie of writes in a single APIC register. On a modern intel machine IPIs travels on the system bus. The periferals located on the PCI bus send MSI (Message Signalled Interrupts) to locals APICs. These interruptions are done with a write at a specific address. >From Intel Manual volume 3B chapter 29 "APIC virtualization" ------------------------------------------------------------ APIC-V allow each VM to have a partially virtualized APIC in order to reduce the number of vmexits (going back from the vm code to the hypervisor code). Intel marketing is talking about a reduction by 50% of the vm exits count. As a consequence of APIC-V IO performance should go up. A 4KB page looking like the one of a local APIC is available for the guest to use. Depending on the specific access type done by the guest in this 4KB page some vmexit will be triggered in order to emulate the access or the access will be virtualized without vmexit. Interrupts can be posted by the hypervisor in a descriptor so the guest receive the interrupt without a vm exit.This is called Posted Interrupts. The hardware is not available yet and the posted interrupt code is currently being written (probably around/after 2.6.10) Looking for the best way to contribute -------------------------------------- As it's seems too early to benchmark APIC-V I am looking the the best way I could take to help improve $customer block IO performance with my current skill set which is mainly fiddling qemu block drivers. Best regards Benoît -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
