Hi, On Thu, Oct 18, 2012 at 02:33:02PM +0200, Avi Kivity wrote: > On 10/18/2012 11:27 AM, Vasilis Liaskovitis wrote: > > On Wed, Oct 17, 2012 at 12:03:51PM +0200, Avi Kivity wrote: > >> On 10/17/2012 11:19 AM, Vasilis Liaskovitis wrote: > >> >> > >> >> I don't think so, but probably there's a limit of DIMMs that real > >> >> controllers have, something like 8 max. > >> > > >> > In the case of i440fx specifically, do you mean that we should model the DRB > >> > (Dram row boundary registers in section 3.2.19 of the i440fx spec) ? > >> > > >> > The i440fx DRB registers only supports up to 8 DRAM rows (let's say 1 row > >> > maps 1-1 to a DimmDevice for this discussion) and only supports up to 2GB of > >> > memory afaict (bit 31 and above is ignored). > >> > > >> > I 'd rather not model this part of the i440fx - having only 8 DIMMs seems too > >> > restrictive. The rest of the patchset supports up to 255 DIMMs so it would be a > >> > waste imho to model an old pc memory controller that only supports 8 DIMMs. > >> > > >> > There was also an old discussion about i440fx modeling here: > >> > https://lists.nongnu.org/archive/html/qemu-devel/2011-07/msg02705.html > >> > the general direction was that i440fx is too old and we don't want to precisely > >> > emulate the DRB registers, since they lack flexibility. > >> > > >> > Possible solutions: > >> > > >> > 1) is there a newer and more flexible chipset that we could model? > >> > >> Look for q35 on this list. > > > > thanks, I 'll take a look. It sounds like the other options below are more > > straightforward now, but let me know if you prefer q35 integration as a priority. > > At least validate that what you're doing fits with how q35 works. In terms of pmc modeling, the q35 page http://wiki.qemu.org/Features/Q35 mentions: Refactor i440fx to create i440fx-pmc class ich9: model ICH9 Super I/O chip ich9: make i440fx-pmc a generic PCNorthBridge class and add support for ich9 northbridge is this still the plan? There was an old patchset creating i440fx-pmc here: http://lists.gnu.org/archive/html/qemu-devel/2012-01/msg03501.html but I am not sure if it has been dropped or worked on. v3 of the q35 patchset doesn't include a pmc I think. It would be good to know what the current plan regarding pmc modeling (for both q35 and i440fx) is. thanks, - Vasilis -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
