Peter Maydell <peter.maydell@xxxxxxxxxx> writes:
> On 29 August 2012 00:37, Rusty Russell <rusty.russell@xxxxxxxxxx> wrote:
>> This compiles, completely untested, but it's my attempt to give
>> Avi (and Alexander) what he asked for in a generic register accessor.
>>
>> Mingled in these patches is the conversion of the latest KVM ARM code,
>> which is the first proposed user: by the end, we use these accessors for
>> *every* register and piece of state.
>>
>> GET_MULTI/SET_MULTI is an obvious extension which is not yet
>> implemented.
>
> Hi Rusty.
>
> I don't see any api.txt patches in here, did I miss them?
> (your cover letter doesn't include a diffstat...)
>
> I don't particularly have comments on the implementation but I would
> like to see the kernel-userspace ABI clearly described rather than
> having to infer it from the code. (including the complete set of
> index mappings for the ARM registers that will use this)
It would look something like this:
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 19d8915..c0453d7 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -293,7 +293,7 @@ kvm_run' (see below).
4.11 KVM_GET_REGS
Capability: basic
-Architectures: all
+Architectures: all except ARM
Type: vcpu ioctl
Parameters: struct kvm_regs (out)
Returns: 0 on success, -1 on error
@@ -314,7 +314,7 @@ struct kvm_regs {
4.12 KVM_SET_REGS
Capability: basic
-Architectures: all
+Architectures: all except ARM
Type: vcpu ioctl
Parameters: struct kvm_regs (in)
Returns: 0 on success, -1 on error
@@ -1733,6 +1733,17 @@ registers, find a list below:
| |
PPC | KVM_REG_PPC_HIOR | 64
+ARM registers are mapped using the lower 32 bits. The upper 16 of that
+is the coprocessor number (or 16 for core registers):
+
+ARM 32-bit CP15 registers have the following id bit patterns:
+ 0x4002 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>
+
+ARM 64-bit CP15 registers have the following id bit patterns:
+ 0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>
+
+ARM core registers have the following id format:
+ 0x4003 0000 0010 <offset in struct kvm_regs, divided by 4>
4.69 KVM_GET_ONE_REG
@@ -1986,50 +1997,26 @@ the virtualized real-mode area (VRMA) facility, the kernel will
re-create the VMRA HPTEs on the next KVM_RUN of any vcpu.)
-4.76 KVM_VCPU_GET_MSR_INDEX_LIST
+4.76 KVM_VCPU_GET_REG_LIST
-Capability: basic
+Capability: KVM_CAP_REG_LIST
Architectures: arm
Type: vcpu ioctl
-Parameters: struct kvm_msr_list (in/out)
+Parameters: struct kvm_reg_list (in/out)
Returns: 0 on success; -1 on error
Errors:
- E2BIG: the msr index list is too big to fit in the array specified by
- the user.
+ E2BIG: the reg index list is too big to fit in the array specified by
+ the user (the number required will be written into n).
struct kvm_msr_list {
- __u32 nmsrs; /* number of msrs in entries */
- __u32 indices[0];
+ __u64 n; /* number of registers in reg[] */
+ __u64 reg[0];
};
-This ioctl returns the guest special registers that are supported, and
-is only valid after KVM_ARM_VCPU_INIT has been performed to initialize
-the vcpu type and features. It is otherwise the equivalent of the
-x86-specific KVM_GET_MSR_INDEX_LIST, for arm's coprocessor registers
-and other non-register state.
-
-The numbering for the indices for coprocesors is simple: the upper 16
-bits are the coprocessor number. If it's > 15, it's something else,
-for future expansion.
-
-Bit 15 indicates a 64-bit register. For 64 bit registers the bottom 4
-bits are CRm, the next 4 are opc1 (just like the MCRR/MRCC instruction
-encoding). For 32 bit registers, the bottom 4 bits are CRm, the next
-3 are opc2, the next 4 CRn, and the next 3 opc1 (the same order as the
-MRC/MCR instruction encoding, but not the same bit positions).
-
-64-bit coprocessor register:
- ...|19 18 17 16|15|14 13 12 11 10 9 8| 7 6 5 4 |3 2 1 0|
- ...0 0 | cp num | 1| 0 0 0 0 0 0 0| opc1 | CRm |
-
-32-bit coprocessor register:
- ...|19 18 17 16|15|14|13 12 11|10 9 8 7 |6 5 4 |3 2 1 0|
- ...0 0 | cp num | 0| 0| opc1 | CRn | opc2 | CRm |
-
-Non-coprocessor register:
-
- | 32 31 30 29 28 27 26 25 24 23 22 21 20|19 18 17 16 15 ...
- | < some non-zero value > | ...
+This ioctl returns the guest registers that are supported for the
+KVM_GET_ONE_REG/KVM_SET_ONE_REG calls, and is only valid after
+KVM_ARM_VCPU_INIT has been performed to initialize the vcpu type and
+features.
4.77 KVM_ARM_VCPU_INIT
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