On Tue, Jul 24, 2012 at 09:40:26AM -0300, Marcelo Tosatti wrote:
>
> On Tue, Jul 24, 2012 at 03:35:14PM +0300, Gleb Natapov wrote:
> > Ping. Is some additional work expected from me before this is applied?
>
> Still not clear to me why its safe to skip kvm_apic_accept_pic_intr check
> before calling ack notifier.
>
I do not think it is actually.
> > On Tue, Jul 17, 2012 at 02:59:11PM +0300, Gleb Natapov wrote:
> > > After commit 242ec97c358256 PIT interrupts are no longer delivered after
> > > PIC reset. It happens because PIT injects interrupt only if previous one
> > > was acked, but since on PIC reset it is dropped from irr it will never
> > > be delivered and hence acknowledged. Fix that by calling ack notifier on
> > > PIC reset.
> > >
> > > Signed-off-by: Gleb Natapov <gleb@xxxxxxxxxx>
> > > diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
> > > index 81cf4fa..f09e790 100644
> > > --- a/arch/x86/kvm/i8259.c
> > > +++ b/arch/x86/kvm/i8259.c
> > > @@ -305,6 +305,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
> > > addr &= 1;
> > > if (addr == 0) {
> > > if (val & 0x10) {
> > > + u8 edge_irr = s->irr & ~s->elcr;
> > > s->init4 = val & 1;
> > > s->last_irr = 0;
> > > s->irr &= s->elcr;
> > > @@ -322,6 +323,9 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
> > > if (val & 0x08)
> > > pr_pic_unimpl(
> > > "level sensitive irq not supported");
> > > + for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
> > > + if (edge_irr & (1 << irq))
> > > + pic_clear_isr(s, irq);
> > > } else if (val & 0x08) {
> > > if (val & 0x04)
> > > s->poll = 1;
> > > --
> > > Gleb.
> > > --
--
Gleb.
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