On 25.06.2012, at 14:26, Mihai Caraman wrote: > Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits. > Change get tlb eaddr to use this mask. Please see section 6.11.4.8 in the PowerISA 2.06b: MMU behavior is largely unaffected by whether the thread is in 32-bit computation mode (MSRCM=0) or 64- bit computation mode (MSRCM=1). The only differ- ences occur in the EPN field of the TLB entry and the EPN field of MAS2. The differences are summarized here. • Executing a tlbwe instruction in 32-bit mode will set bits 0:31 of the TLB EPN field to zero unless MAS0ATSEL is set, in which case those bits are not written to zero. • In 32-bit implementations, MAS2U can be used to read or write EPN0:31 of MAS2. So if MSR.CM is not set tlbwe should mask the upper 32 bits out - which can happen regardless of CONFIG_64BIT. Also, we need to implement MAS2U, to potentially make the upper 32bits of MAS2 available, right? But that one isn't as important as the first bit. Alex -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
