On 2012-06-07 09:51, Abel Gordon wrote: >> 3> if we configure not exit on external interrupt by setting some >> field in VMCS, what will happen during the physical interrupts? will >> the CPU use the guest IDT for response interrupt? If so, can KVM >> redirect the CPU to use another IDT for guest (assuming modifying the >> IDTR)? > > Yes, that's exactly something we already did in a research project. > You can read our paper published in ASPLOS 2012: ELI: Bare-metal > performance for I/O virtualization > ( > http://dl.acm.org/citation.cfm?id=2151020&dl=ACM&coll=DL&CFID=86701665&CFTOKEN=26302003 Interesting. Can you provide it publicly (or send a version privately)? > ) > > Note this is not so simple, there are many other issues you should > consider. Is it just complicated, not upstreamable, or are the unsolved issues like security holes or the need to paravirtualize the guest? I'm still hoping that Intel/AMD will finally enable this in hardware, at least for MSIs. Providing direct injection for legacy line-base interrupts is likely not worth the silicon and bits (would require some hw-assisted IOAPIC instead of just a bit more APIC virtualization). Jan
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