On 17/05/12 13:00, Benjamin Herrenschmidt wrote: > On Thu, 2012-05-17 at 12:16 +1000, Alexey Kardashevskiy wrote: > >>> It actually can change dynamically on x86 due to acpi interrupt links >>> which allow the guest a generic way to select from a set of possible >>> interrupt routing schemes. And of course a chipset driver could twiddle >>> bits if it wanted as well. So, we really do need the update notifiers >>> from my tree that this patch drops. >> >> >> You mean notifiers like these: ioapic_add_gsi_eoi_notifier? >> I did not drop them, we need them so I implemented them for XICS interrupt controller. > > So I haven't completely understood the problem, however: > > .../... > >> So it stores global IRQs in the config space but it really unclear who writes these _global_ numbers >> there. Is it the guest who allocates IRQs and writes the numbers into the config space so QEMU knows >> what pin is what IRQ? If so, I am wrong, you are right :) > > So you can certainly not write our global irq numbers in the config > space, since the config space IRQ_LINE register is only 8 bits long > which means it's not long enough. [had a char] No, it is all about piix3 extended capability. -- Alexey -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
