Avoid the slow-path MSI delivery via stl_phys by switching to
msi_deliver. This also allows to prepare these rarely changing messages
in advance.
Signed-off-by: Jan Kiszka <jan.kiszka@xxxxxxxxxxx>
---
hw/hpet.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/hw/hpet.c b/hw/hpet.c
index d8e6b8e..c6d6e35 100644
--- a/hw/hpet.c
+++ b/hw/hpet.c
@@ -31,6 +31,7 @@
#include "hpet_emul.h"
#include "sysbus.h"
#include "mc146818rtc.h"
+#include "msi.h"
//#define HPET_DEBUG
#ifdef HPET_DEBUG
@@ -55,6 +56,8 @@ typedef struct HPETTimer { /* timers */
uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
* mode. Next pop will be actual timer expiration.
*/
+ MSIMessage msi_msg;
+ MSIRoutingCache msi_cache;
} HPETTimer;
typedef struct HPETState {
@@ -192,7 +195,7 @@ static void update_irq(struct HPETTimer *timer, int set)
qemu_irq_lower(s->irqs[route]);
}
} else if (timer_fsb_route(timer)) {
- stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
+ msi_deliver(&timer->msi_msg, &timer->msi_cache);
} else if (timer->config & HPET_TN_TYPE_LEVEL) {
s->isr |= mask;
qemu_irq_raise(s->irqs[route]);
@@ -533,9 +536,11 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
break;
case HPET_TN_ROUTE:
timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
+ timer->msi_msg.data = new_val;
break;
case HPET_TN_ROUTE + 4:
timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
+ timer->msi_msg.address = new_val;
break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");
--
1.7.3.4
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