On 10/04/2011 07:24 PM, Jan Kiszka wrote:
>> >> Given that, when in conflict, we rather model after AMD than Intel for >> TCG, I would hesitate to expose this by default. Or are there >> precedences already? > > Practically all MSRs. i486 doesn't have any, IIRC, for example. Pre-Pentiums don't have instructions to access them as well, so that doesn't cause any harm.
kvm doesn't detect this; does tcg? In any case, MSR availability varies widely with processor model.
> > (and given this MSR has no effect, the only difference it makes to > guests is the #GP we take or not; still it may be worthwhile to > construct some table-driven thing to allow or reject MSR accesses, both > for kvm and qemu) Right. If this MSR is not the first bogus one on AMD, we can do this later. If it is, it should be done first.
It's certainly not the first - they practically all are, depending on exact model.
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