Marcelo Tosatti wrote:
>> + } else if (apic_lvtt_tscdeadline(apic)) {
>> + /* lapic timer in tsc deadline mode */
>> + u64 guest_tsc, guest_tsc_delta, ns = 0;
>> + struct kvm_vcpu *vcpu = apic->vcpu;
>> + unsigned long this_tsc_khz = vcpu_tsc_khz(vcpu); + unsigned long
>> flags; +
>> + if (unlikely(!apic->lapic_timer.tscdeadline || !this_tsc_khz))
>> + return; +
>> + local_irq_save(flags);
>> +
>> + now = apic->lapic_timer.timer.base->get_time();
>> + kvm_get_msr(vcpu, MSR_IA32_TSC, &guest_tsc);
>
> Use kvm_x86_ops->read_l1_tsc(vcpu) instead of direct MSR read
> (to avoid reading L2 guest TSC in case of nested virt).
>
>> + guest_tsc_delta = apic->lapic_timer.tscdeadline - guest_tsc;
>
> if (guest_tsc <= tscdeadline), the timer should start immediately.
>
Yes, under such case the timer does start immediately, with ns = 0
Thanks,
Jinsong--
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