On Tue, 2011-09-06 at 11:05 +0200, Jan Kiszka wrote: > On 2011-09-06 11:00, Sasha Levin wrote: > > On Tue, 2011-09-06 at 10:49 +0200, Jan Kiszka wrote: > >> On 2011-09-06 10:46, Sasha Levin wrote: > >>> On Tue, 2011-09-06 at 10:36 +0200, Jan Kiszka wrote: > >>>> On 2011-09-06 10:12, Michael S. Tsirkin wrote: > >>>>> On Tue, Sep 06, 2011 at 10:52:41AM +0300, Avi Kivity wrote: > >>>>>>> > >>>>>>> BTW, the same is also true for that optional per-vector masking of > >>>>>>> legacy MSI. Are there devices in the field that actually support this? I > >>>>>>> haven't found one so far and tend to consider this feature not worth > >>>>>>> implementing. > >>>>>> > >>>>>> Don't know. I don't like implementing features on the basis of bug > >>>>>> reports, though. On the other hand we can't really test it without > >>>>>> a real device. > >>>>> > >>>>> Linux will use this capability if present. So > >>>>> we could add support for an emulated device (e.g. e1000), > >>>>> then test with nested virt once iommu emulation lands :) > >>>> > >>>> Yeah, would be kind of cool. Still, I would feel better having it tested > >>>> against a real silicon as well. Also to prove that there is a real need. > >>>> > >>>> So, in case someone stumbles for such a device (bit 8 set in MSI control > >>>> word), please let us know! > >>> > >>> Doesn't any device that supports MSI-X supports per-vector masking? > >>> > >>> >From the spec: > >>> > >>> "MSI and MSI-X each support per-vector masking. Per-vector masking is an > >>> optional extension to MSI, and a standard feature with MSI-X" > >> > >> Right, but the cap flag still has to be set. > >> > > > > Are you sure? Take a look at the table in section 6.8.2.3 in the spec > > (pci v3). Unlike the message control for MSI, this table doesn't mention > > anything about bit 8 or the per-vector masking capability for MSI-X, it > > just assumes it's there. > > [Err, I should stop doing n things in parallel.] > > Of course, MSI-X implies per-vector masking, but in a totally different > way with different data structures etc. That's not interesting for the > case in question: per-vector masking for legacy MSI. > Ah, Okay. > Back to square #1: We need a device with MSI support and cap bit 8 set > in its _MSI_ control word. Alright, so I've looked at some of my servers, and one of them has both a bunch of MSI-X devices, and some MSI devices which show this: Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: 00000020 Data: 0000 Masking: 00000000 Pending: 00000000 Which would suggest that the support per-vector masking, right? -- Sasha. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
