Convert all vga memory to the memory API. Note we need to fall back to
get_system_memory(), since the various buses don't pass the vga window
as a memory region.
Signed-off-by: Avi Kivity <avi@xxxxxxxxxx>
---
hw/cirrus_vga.c | 346 +++++++++++++++++++++++++++++++++----------------------
hw/vga-isa-mm.c | 66 ++++++++---
hw/vga-isa.c | 13 ++-
hw/vga-pci.c | 28 +----
hw/vga.c | 146 +++++++++++-------------
hw/vga_int.h | 20 ++--
hw/vmware_vga.c | 84 ++++++++-----
7 files changed, 395 insertions(+), 308 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index f39d1f8..0cce453 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -200,9 +200,14 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
typedef struct CirrusVGAState {
VGACommonState vga;
- int cirrus_linear_io_addr;
- int cirrus_linear_bitblt_io_addr;
- int cirrus_mmio_io_addr;
+ MemoryRegion cirrus_linear_io;
+ MemoryRegion cirrus_linear_bitblt_io;
+ MemoryRegion cirrus_mmio_io;
+ MemoryRegion pci_bar;
+ bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
+ MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
+ MemoryRegion low_mem; /* always mapped, overridden by: */
+ MemoryRegion *cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
uint32_t cirrus_addr_mask;
uint32_t linear_mmio_mask;
uint8_t cirrus_shadow_gr0;
@@ -612,7 +617,7 @@ static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
off_cur &= TARGET_PAGE_MASK;
while (off_cur < off_cur_end) {
- cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
+ memory_region_set_dirty(&s->vga.vram, off_cur);
off_cur += TARGET_PAGE_SIZE;
}
off_begin += off_pitch;
@@ -1177,12 +1182,6 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
}
if (limit > 0) {
- /* Thinking about changing bank base? First, drop the dirty bitmap information
- * on the current location, otherwise we lose this pointer forever */
- if (s->vga.lfb_vram_mapped) {
- target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
- cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
- }
s->cirrus_bank_base[bank_index] = offset;
s->cirrus_bank_limit[bank_index] = limit;
} else {
@@ -1921,8 +1920,8 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
val <<= 1;
dst++;
}
- cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
- cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
+ memory_region_set_dirty(&s->vga.vram, offset);
+ memory_region_set_dirty(&s->vga.vram, offset + 7);
}
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
@@ -1946,8 +1945,8 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
val <<= 1;
dst += 2;
}
- cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
- cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
+ memory_region_set_dirty(&s->vga.vram, offset);
+ memory_region_set_dirty(&s->vga.vram, offset + 15);
}
/***************************************
@@ -2057,8 +2056,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
mode = s->vga.gr[0x05] & 0x7;
if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
*(s->vga.vram_ptr + bank_offset) = mem_value;
- cpu_physical_memory_set_dirty(s->vga.vram_offset +
- bank_offset);
+ memory_region_set_dirty(&s->vga.vram, bank_offset);
} else {
if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
cirrus_mem_writeb_mode4and5_8bpp(s, mode,
@@ -2099,16 +2097,37 @@ static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_
cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
-static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
- cirrus_vga_mem_readb,
- cirrus_vga_mem_readw,
- cirrus_vga_mem_readl,
+static uint64_t cirrus_vga_mem_read(MemoryRegion *mr,
+ target_phys_addr_t addr,
+ uint32_t size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState, low_mem);
+
+ switch (size) {
+ case 1: return cirrus_vga_mem_readb(s, addr);
+ case 2: return cirrus_vga_mem_readw(s, addr);
+ case 4: return cirrus_vga_mem_readl(s, addr);
+ default: abort();
+ }
+}
+
+static void cirrus_vga_mem_write(MemoryRegion *mr, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState, low_mem);
+
+ switch (size) {
+ case 1: return cirrus_vga_mem_writeb(s, addr, data);
+ case 2: return cirrus_vga_mem_writew(s, addr, data);
+ case 4: return cirrus_vga_mem_writel(s, addr, data);
+ default: abort();
+ }
};
-static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
- cirrus_vga_mem_writeb,
- cirrus_vga_mem_writew,
- cirrus_vga_mem_writel,
+static MemoryRegionOps cirrus_vga_mem_ops = {
+ .read = cirrus_vga_mem_read,
+ .write = cirrus_vga_mem_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
/***************************************
@@ -2365,7 +2384,7 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
mode = s->vga.gr[0x05] & 0x7;
if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
*(s->vga.vram_ptr + addr) = (uint8_t) val;
- cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
+ memory_region_set_dirty(&s->vga.vram, addr);
} else {
if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
@@ -2393,17 +2412,31 @@ static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
}
-static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
- cirrus_linear_readb,
- cirrus_linear_readw,
- cirrus_linear_readl,
-};
+static uint64_t cirrus_linear_read(MemoryRegion *mr, target_phys_addr_t addr,
+ unsigned size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState, cirrus_linear_io);
-static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
- cirrus_linear_writeb,
- cirrus_linear_writew,
- cirrus_linear_writel,
-};
+ switch (size) {
+ case 1: return cirrus_linear_readb(s, addr);
+ case 2: return cirrus_linear_readw(s, addr);
+ case 4: return cirrus_linear_readl(s, addr);
+ default: abort();
+ }
+}
+
+static void cirrus_linear_write(MemoryRegion *mr, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState, cirrus_linear_io);
+
+ switch (size) {
+ case 1: return cirrus_linear_writeb(s, addr, data);
+ case 2: return cirrus_linear_writew(s, addr, data);
+ case 4: return cirrus_linear_writel(s, addr, data);
+ default: abort();
+ }
+}
/***************************************
*
@@ -2471,67 +2504,99 @@ static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
+static uint64_t cirrus_linear_bitblt_read(MemoryRegion *mr,
+ target_phys_addr_t addr,
+ unsigned size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState,
+ cirrus_linear_bitblt_io);
-static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
- cirrus_linear_bitblt_readb,
- cirrus_linear_bitblt_readw,
- cirrus_linear_bitblt_readl,
+ switch (size) {
+ case 1: return cirrus_linear_bitblt_readb(s, addr);
+ case 2: return cirrus_linear_bitblt_readw(s, addr);
+ case 4: return cirrus_linear_bitblt_readl(s, addr);
+ default: abort();
+ }
};
-static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
- cirrus_linear_bitblt_writeb,
- cirrus_linear_bitblt_writew,
- cirrus_linear_bitblt_writel,
+static void cirrus_linear_bitblt_write(MemoryRegion *mr,
+ target_phys_addr_t addr,
+ uint64_t data,
+ unsigned size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState,
+ cirrus_linear_bitblt_io);
+
+ switch (size) {
+ case 1: return cirrus_linear_bitblt_writeb(s, addr, data);
+ case 2: return cirrus_linear_bitblt_writew(s, addr, data);
+ case 4: return cirrus_linear_bitblt_writel(s, addr, data);
+ default: abort();
+ }
};
-static void map_linear_vram(CirrusVGAState *s)
+static MemoryRegionOps cirrus_linear_bitblt_io_ops = {
+ .read = cirrus_linear_bitblt_read,
+ .write = cirrus_linear_bitblt_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+#include "exec-memory.h"
+
+static void unmap_bank(CirrusVGAState *s, unsigned bank)
{
- if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
- s->vga.map_addr = s->vga.lfb_addr;
- s->vga.map_end = s->vga.lfb_end;
- cpu_register_physical_memory_log(s->vga.map_addr,
- s->vga.map_end - s->vga.map_addr,
- s->vga.vram_offset, 0, true);
+ if (s->cirrus_bank[bank]) {
+ memory_region_del_subregion(&s->low_mem_container,
+ s->cirrus_bank[bank]);
+ memory_region_destroy(s->cirrus_bank[bank]);
+ qemu_free(s->cirrus_bank[bank]);
+ s->cirrus_bank[bank] = NULL;
}
+}
- if (!s->vga.map_addr)
- return;
-
- s->vga.lfb_vram_mapped = 0;
+static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
+{
+ MemoryRegion *mr;
+ static const char *names[] = { "vga.bank0", "vga.bank1" };
if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
&& !((s->vga.sr[0x07] & 0x01) == 0)
&& !((s->vga.gr[0x0B] & 0x14) == 0x14)
&& !(s->vga.gr[0x0B] & 0x02)) {
- cpu_register_physical_memory_log(isa_mem_base + 0xa0000, 0x8000,
- (s->vga.vram_offset +
- s->cirrus_bank_base[0]) |
- IO_MEM_RAM, 0, true);
- cpu_register_physical_memory_log(isa_mem_base + 0xa8000, 0x8000,
- (s->vga.vram_offset +
- s->cirrus_bank_base[1]) |
- IO_MEM_RAM, 0, true);
-
- s->vga.lfb_vram_mapped = 1;
- }
- else {
- cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
- s->vga.vga_io_memory);
+ mr = qemu_malloc(sizeof(*mr));
+ memory_region_init_alias(mr, names[bank], &s->vga.vram,
+ s->cirrus_bank_base[bank], 0x8000);
+ memory_region_add_subregion_overlap(
+ &s->low_mem_container,
+ 0x8000 * bank,
+ mr,
+ 1);
+ unmap_bank(s, bank);
+ s->cirrus_bank[bank] = mr;
+ } else {
+ unmap_bank(s, bank);
}
+}
- vga_dirty_log_start(&s->vga);
+static void map_linear_vram(CirrusVGAState *s)
+{
+ if (!s->linear_vram) {
+ s->linear_vram = true;
+ memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
+ }
+ map_linear_vram_bank(s, 0);
+ map_linear_vram_bank(s, 1);
}
static void unmap_linear_vram(CirrusVGAState *s)
{
- if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
- s->vga.map_addr = s->vga.map_end = 0;
- cpu_register_physical_memory(s->vga.lfb_addr, s->vga.vram_size,
- s->cirrus_linear_io_addr);
+ if (s->linear_vram) {
+ s->linear_vram = false;
+ memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
}
- cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
- s->vga.vga_io_memory);
+ unmap_bank(s, 0);
+ unmap_bank(s, 1);
}
/* Compute the memory access functions */
@@ -2829,16 +2894,36 @@ static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
}
-static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
- cirrus_mmio_readb,
- cirrus_mmio_readw,
- cirrus_mmio_readl,
+static uint64_t cirrus_mmio_read(MemoryRegion *mr, target_phys_addr_t addr,
+ unsigned size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState, cirrus_mmio_io);
+
+ switch (size) {
+ case 1: return cirrus_mmio_readb(s, addr);
+ case 2: return cirrus_mmio_readw(s, addr);
+ case 4: return cirrus_mmio_readl(s, addr);
+ default: abort();
+ }
};
-static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
- cirrus_mmio_writeb,
- cirrus_mmio_writew,
- cirrus_mmio_writel,
+static void cirrus_mmio_write(MemoryRegion *mr, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+ CirrusVGAState *s = container_of(mr, CirrusVGAState, cirrus_mmio_io);
+
+ switch (size) {
+ case 1: return cirrus_mmio_writeb(s, addr, data);
+ case 2: return cirrus_mmio_writew(s, addr, data);
+ case 4: return cirrus_mmio_writel(s, addr, data);
+ default: abort();
+ }
+};
+
+static MemoryRegionOps cirrus_mmio_io_ops = {
+ .read = cirrus_mmio_read,
+ .write = cirrus_mmio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
/* load/save state */
@@ -2947,6 +3032,12 @@ static void cirrus_reset(void *opaque)
s->cirrus_hidden_dac_data = 0;
}
+static MemoryRegionOps cirrus_linear_io_ops = {
+ .read = cirrus_linear_read,
+ .write = cirrus_linear_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
{
int i;
@@ -2993,28 +3084,32 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
- s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
- cirrus_vga_mem_write, s,
- DEVICE_LITTLE_ENDIAN);
- cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
- s->vga.vga_io_memory);
- qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
+ memory_region_init(&s->low_mem_container,
+ "cirrus-lowmem-container",
+ 0x20000);
+
+ memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops,
+ "cirrus-low-memory", 0x20000);
+ memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ isa_mem_base + 0x000a0000,
+ &s->low_mem_container,
+ 1);
+ memory_region_set_coalescing(&s->low_mem);
/* I/O handler for LFB */
- s->cirrus_linear_io_addr =
- cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s,
- DEVICE_LITTLE_ENDIAN);
+ memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops,
+ "cirrus-linear-io", VGA_RAM_SIZE);
/* I/O handler for LFB */
- s->cirrus_linear_bitblt_io_addr =
- cpu_register_io_memory(cirrus_linear_bitblt_read,
- cirrus_linear_bitblt_write, s,
- DEVICE_LITTLE_ENDIAN);
+ memory_region_init_io(&s->cirrus_linear_bitblt_io,
+ &cirrus_linear_bitblt_io_ops,
+ "cirrus-bitblt-mmio",
+ 0x400000);
/* I/O handler for memory-mapped I/O */
- s->cirrus_mmio_io_addr =
- cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s,
- DEVICE_LITTLE_ENDIAN);
+ memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops,
+ "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
s->real_vram_size =
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
@@ -3060,42 +3155,6 @@ void isa_cirrus_vga_init(void)
*
***************************************/
-static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
- CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
-
- /* XXX: add byte swapping apertures */
- cpu_register_physical_memory(addr, s->vga.vram_size,
- s->cirrus_linear_io_addr);
- cpu_register_physical_memory(addr + 0x1000000, 0x400000,
- s->cirrus_linear_bitblt_io_addr);
-
- s->vga.map_addr = s->vga.map_end = 0;
- s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
- s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
- /* account for overflow */
- if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
- s->vga.lfb_end = addr + VGA_RAM_SIZE;
-
- vga_dirty_log_start(&s->vga);
-}
-
-static void pci_cirrus_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
-{
- PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d);
- CirrusVGAState *s = &pvs->cirrus_vga;
-
- pci_default_write_config(d, address, val, len);
- if (s->vga.map_addr && d->io_regions[0].addr == PCI_BAR_UNMAPPED) {
- s->vga.map_addr = 0;
- s->vga.lfb_addr = 0;
- s->vga.lfb_end = 0;
- }
- cirrus_update_memory_access(s);
-}
-
static int pci_cirrus_vga_initfn(PCIDevice *dev)
{
PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
@@ -3112,15 +3171,23 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
/* setup PCI */
+ memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
+
+ /* XXX: add byte swapping apertures */
+ memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
+ memory_region_add_subregion(&s->pci_bar, 0x1000000,
+ &s->cirrus_linear_bitblt_io);
+
+ vga_dirty_log_start(&s->vga);
+
/* setup memory space */
/* memory #0 LFB */
/* memory #1 memory-mapped I/O */
/* XXX: s->vga.vram_size must be a power of two */
- pci_register_bar(&d->dev, 0, 0x2000000,
- PCI_BASE_ADDRESS_MEM_PREFETCH, cirrus_pci_lfb_map);
+ pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
+ &s->pci_bar);
if (device_id == CIRRUS_ID_CLGD5446) {
- pci_register_bar_simple(&d->dev, 1, CIRRUS_PNPMMIO_SIZE, 0,
- s->cirrus_mmio_io_addr);
+ pci_register_bar_region(&d->dev, 1, 0, &s->cirrus_mmio_io);
}
return 0;
}
@@ -3138,7 +3205,6 @@ static PCIDeviceInfo cirrus_vga_info = {
.no_hotplug = 1,
.init = pci_cirrus_vga_initfn,
.romfile = VGABIOS_CIRRUS_FILENAME,
- .config_write = pci_cirrus_write_config,
.vendor_id = PCI_VENDOR_ID_CIRRUS,
.device_id = CIRRUS_ID_CLGD5446,
.class_id = PCI_CLASS_DISPLAY_VGA,
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index 4954bb1..2d6bedc 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -79,35 +79,67 @@ static void vga_mm_writel (void *opaque,
vga_ioport_write(&s->vga, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc * const vga_mm_read_ctrl[] = {
- &vga_mm_readb,
- &vga_mm_readw,
- &vga_mm_readl,
-};
+static uint64_t vga_mm_read_ctrl(MemoryRegion *mr, target_phys_addr_t addr,
+ unsigned size)
+{
+ VGACommonState *vs = container_of(mr, VGAMemoryRegion, mem)->s;
+ ISAVGAMMState *s = container_of(vs, ISAVGAMMState, vga);
+
+ switch (size) {
+ case 1: return vga_mm_readb(s, addr);
+ case 2: return vga_mm_readw(s, addr);
+ case 4: return vga_mm_readl(s, addr);
+ default: abort();
+ }
+}
+
+static void vga_mm_write_ctrl(MemoryRegion *mr, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+ VGACommonState *vs = container_of(mr, VGAMemoryRegion, mem)->s;
+ ISAVGAMMState *s = container_of(vs, ISAVGAMMState, vga);
+
+ switch (size) {
+ case 1: return vga_mm_writeb(s, addr, data);
+ case 2: return vga_mm_writew(s, addr, data);
+ case 4: return vga_mm_writel(s, addr, data);
+ default: abort();
+ }
+}
-static CPUWriteMemoryFunc * const vga_mm_write_ctrl[] = {
- &vga_mm_writeb,
- &vga_mm_writew,
- &vga_mm_writel,
+static MemoryRegionOps vga_mm_ctrl_ops = {
+ .read = vga_mm_read_ctrl,
+ .write = vga_mm_write_ctrl,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
+#include "exec-memory.h"
+
static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift)
{
- int s_ioport_ctrl, vga_io_memory;
+ VGAMemoryRegion *s_ioport_ctrl, *vga_io_memory;
s->it_shift = it_shift;
- s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s,
- DEVICE_NATIVE_ENDIAN);
- vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s,
- DEVICE_NATIVE_ENDIAN);
+ s_ioport_ctrl = qemu_malloc(sizeof(*s_ioport_ctrl));
+ memory_region_init_io(&s_ioport_ctrl->mem, &vga_mm_ctrl_ops, "vga-mm-ctrl",
+ 0x100000);
+ s_ioport_ctrl->s = &s->vga;
+
+ vga_io_memory = qemu_malloc(sizeof(*vga_io_memory));
+ /* XXX: endianness? */
+ memory_region_init_io(&vga_io_memory->mem, &vga_mem_ops, "vga-mem",
+ 0x20000);
+ vga_io_memory->s = &s->vga;
vmstate_register(NULL, 0, &vmstate_vga_common, s);
- cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
+ memory_region_add_subregion(get_system_memory(), ctrl_base,
+ &s_ioport_ctrl->mem);
s->vga.bank_offset = 0;
- cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
- qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
+ memory_region_add_subregion(get_system_memory(),
+ vram_base + 0x000a0000, &vga_io_memory->mem);
+ memory_region_set_coalescing(&vga_io_memory->mem);
}
int isa_vga_mm_init(target_phys_addr_t vram_base,
diff --git a/hw/vga-isa.c b/hw/vga-isa.c
index 245841f..9fd282a 100644
--- a/hw/vga-isa.c
+++ b/hw/vga-isa.c
@@ -42,17 +42,22 @@ static void vga_reset_isa(DeviceState *dev)
vga_common_reset(s);
}
+#include "exec-memory.h"
+
static int vga_initfn(ISADevice *dev)
{
ISAVGAState *d = DO_UPCAST(ISAVGAState, dev, dev);
VGACommonState *s = &d->state;
- int vga_io_memory;
+ VGAMemoryRegion *vga_io_memory;
vga_common_init(s, VGA_RAM_SIZE);
vga_io_memory = vga_init_io(s);
- cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
- vga_io_memory);
- qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
+ memory_region_add_subregion_overlap(
+ get_system_memory(),
+ isa_mem_base + 0x000a0000,
+ &vga_io_memory->mem,
+ 1);
+ memory_region_set_coalescing(&vga_io_memory->mem);
isa_init_ioport(dev, 0x3c0);
isa_init_ioport(dev, 0x3b4);
isa_init_ioport(dev, 0x3ba);
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index 481f448..7062c4d 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -47,29 +47,6 @@ static const VMStateDescription vmstate_vga_pci = {
}
};
-static void vga_map(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
- PCIVGAState *d = (PCIVGAState *)pci_dev;
- VGACommonState *s = &d->vga;
-
- cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
- s->map_addr = addr;
- s->map_end = addr + s->vram_size;
- vga_dirty_log_start(s);
-}
-
-static void pci_vga_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
-{
- PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
- VGACommonState *s = &pvs->vga;
-
- pci_default_write_config(d, address, val, len);
- if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
- s->map_addr = 0;
-}
-
static int pci_vga_initfn(PCIDevice *dev)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
@@ -83,8 +60,8 @@ static int pci_vga_initfn(PCIDevice *dev)
s->screen_dump, s->text_update, s);
/* XXX: VGA_RAM_SIZE must be a power of two */
- pci_register_bar(&d->dev, 0, VGA_RAM_SIZE,
- PCI_BASE_ADDRESS_MEM_PREFETCH, vga_map);
+ pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
+ &s->vram);
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */
@@ -106,7 +83,6 @@ static PCIDeviceInfo vga_info = {
.qdev.vmsd = &vmstate_vga_pci,
.no_hotplug = 1,
.init = pci_vga_initfn,
- .config_write = pci_vga_write_config,
.romfile = "vgabios-stdvga.bin",
/* dummy VGA (same as Bochs ID) */
diff --git a/hw/vga.c b/hw/vga.c
index 0f54734..7f7aeb1 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -825,7 +825,7 @@ void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
#endif
s->plane_updated |= mask; /* only used to detect font change */
- cpu_physical_memory_set_dirty(s->vram_offset + addr);
+ memory_region_set_dirty(&s->vram, addr);
}
} else if (s->gr[5] & 0x10) {
/* odd/even mode (aka text mode mapping) */
@@ -838,7 +838,7 @@ void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
#endif
s->plane_updated |= mask; /* only used to detect font change */
- cpu_physical_memory_set_dirty(s->vram_offset + addr);
+ memory_region_set_dirty(&s->vram, addr);
}
} else {
/* standard VGA latched access */
@@ -912,7 +912,7 @@ void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
addr * 4, write_mask, val);
#endif
- cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
+ memory_region_set_dirty(&s->vram, addr << 2);
}
}
@@ -1553,57 +1553,17 @@ void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
static void vga_sync_dirty_bitmap(VGACommonState *s)
{
- if (s->map_addr)
- cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
-
- if (s->lfb_vram_mapped) {
- cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
- cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
- }
-
-#ifdef CONFIG_BOCHS_VBE
- if (s->vbe_mapped) {
- cpu_physical_sync_dirty_bitmap(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
- VBE_DISPI_LFB_PHYSICAL_ADDRESS + s->vram_size);
- }
-#endif
-
+ memory_region_sync_dirty_bitmap(&s->vram);
}
void vga_dirty_log_start(VGACommonState *s)
{
- if (s->map_addr) {
- cpu_physical_log_start(s->map_addr, s->map_end - s->map_addr);
- }
-
- if (s->lfb_vram_mapped) {
- cpu_physical_log_start(isa_mem_base + 0xa0000, 0x8000);
- cpu_physical_log_start(isa_mem_base + 0xa8000, 0x8000);
- }
-
-#ifdef CONFIG_BOCHS_VBE
- if (s->vbe_mapped) {
- cpu_physical_log_start(VBE_DISPI_LFB_PHYSICAL_ADDRESS, s->vram_size);
- }
-#endif
+ memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
}
void vga_dirty_log_stop(VGACommonState *s)
{
- if (s->map_addr) {
- cpu_physical_log_stop(s->map_addr, s->map_end - s->map_addr);
- }
-
- if (s->lfb_vram_mapped) {
- cpu_physical_log_stop(isa_mem_base + 0xa0000, 0x8000);
- cpu_physical_log_stop(isa_mem_base + 0xa8000, 0x8000);
- }
-
-#ifdef CONFIG_BOCHS_VBE
- if (s->vbe_mapped) {
- cpu_physical_log_stop(VBE_DISPI_LFB_PHYSICAL_ADDRESS, s->vram_size);
- }
-#endif
+ memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
}
void vga_dirty_log_restart(VGACommonState *s)
@@ -1773,15 +1733,16 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
if (!(s->cr[0x17] & 2)) {
addr = (addr & ~0x8000) | ((y1 & 2) << 14);
}
- page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
- page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
+ page0 = addr & TARGET_PAGE_MASK;
+ page1 = (addr + bwidth - 1) & TARGET_PAGE_MASK;
update = full_update |
- cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
- cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
+ memory_region_get_dirty(&s->vram, page0, DIRTY_MEMORY_VGA) |
+ memory_region_get_dirty(&s->vram, page1, DIRTY_MEMORY_VGA);
if ((page1 - page0) > TARGET_PAGE_SIZE) {
/* if wide line, can use another page */
- update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
- VGA_DIRTY_FLAG);
+ update |= memory_region_get_dirty(&s->vram,
+ page0 + TARGET_PAGE_SIZE,
+ DIRTY_MEMORY_VGA);
}
/* explicit invalidation for the hardware cursor */
update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
@@ -1826,8 +1787,10 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
}
/* reset modified pages */
if (page_max >= page_min) {
- cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
- VGA_DIRTY_FLAG);
+ memory_region_reset_dirty(&s->vram,
+ page_min,
+ page_max + TARGET_PAGE_SIZE - page_min,
+ DIRTY_MEMORY_VGA);
}
memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
}
@@ -1906,11 +1869,6 @@ static void vga_invalidate_display(void *opaque)
void vga_common_reset(VGACommonState *s)
{
- s->lfb_addr = 0;
- s->lfb_end = 0;
- s->map_addr = 0;
- s->map_end = 0;
- s->lfb_vram_mapped = 0;
s->sr_index = 0;
memset(s->sr, '\0', sizeof(s->sr));
s->gr_index = 0;
@@ -2141,16 +2099,36 @@ static void vga_update_text(void *opaque, console_ch_t *chardata)
dpy_update(s->ds, 0, 0, s->last_width, height);
}
-CPUReadMemoryFunc * const vga_mem_read[3] = {
- vga_mem_readb,
- vga_mem_readw,
- vga_mem_readl,
-};
+static uint64_t vga_mem_read(MemoryRegion *mr, target_phys_addr_t addr,
+ unsigned size)
+{
+ VGACommonState *s = container_of(mr, VGAMemoryRegion, mem)->s;
+
+ switch (size) {
+ case 1: return vga_mem_readb(s, addr);
+ case 2: return vga_mem_readw(s, addr);
+ case 4: return vga_mem_readl(s, addr);
+ default: abort();
+ }
+}
-CPUWriteMemoryFunc * const vga_mem_write[3] = {
- vga_mem_writeb,
- vga_mem_writew,
- vga_mem_writel,
+static void vga_mem_write(MemoryRegion *mr, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+ VGACommonState *s = container_of(mr, VGAMemoryRegion, mem)->s;
+
+ switch (size) {
+ case 1: return vga_mem_writeb(s, addr, data);
+ case 2: return vga_mem_writew(s, addr, data);
+ case 4: return vga_mem_writel(s, addr, data);
+ default: abort();
+ }
+}
+
+MemoryRegionOps vga_mem_ops = {
+ .read = vga_mem_read,
+ .write = vga_mem_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static int vga_common_post_load(void *opaque, int version_id)
@@ -2236,8 +2214,8 @@ void vga_common_init(VGACommonState *s, int vga_ram_size)
#else
s->is_vbe_vmstate = 0;
#endif
- s->vram_offset = qemu_ram_alloc(NULL, "vga.vram", vga_ram_size);
- s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
+ memory_region_init_ram(&s->vram, NULL, "vga.vram", vga_ram_size);
+ s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
s->vram_size = vga_ram_size;
s->get_bpp = vga_get_bpp;
s->get_offsets = vga_get_offsets;
@@ -2260,8 +2238,10 @@ void vga_common_init(VGACommonState *s, int vga_ram_size)
}
/* used by both ISA and PCI */
-int vga_init_io(VGACommonState *s)
+VGAMemoryRegion *vga_init_io(VGACommonState *s)
{
+ VGAMemoryRegion *vga_mem;
+
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
@@ -2292,30 +2272,38 @@ int vga_init_io(VGACommonState *s)
#endif
#endif /* CONFIG_BOCHS_VBE */
- return cpu_register_io_memory(vga_mem_read, vga_mem_write, s,
- DEVICE_LITTLE_ENDIAN);
+ vga_mem = qemu_malloc(sizeof(*vga_mem));
+ memory_region_init_io(&vga_mem->mem, &vga_mem_ops, "vga-lowmem", 0x20000);
+ vga_mem->s = s;
+
+ return vga_mem;
}
+#include "exec-memory.h"
+
void vga_init(VGACommonState *s)
{
- int vga_io_memory;
+ VGAMemoryRegion *vga_io_memory;
qemu_register_reset(vga_reset, s);
s->bank_offset = 0;
vga_io_memory = vga_init_io(s);
- cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
- vga_io_memory);
- qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ isa_mem_base + 0x000a0000,
+ &vga_io_memory->mem,
+ 1);
+ memory_region_set_coalescing(&vga_io_memory->mem);
}
void vga_init_vbe(VGACommonState *s)
{
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
- cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
- VGA_RAM_SIZE, s->vram_offset);
+ memory_region_add_subregion(get_system_memory(),
+ VBE_DISPI_LFB_PHYSICAL_ADDRESS,
+ &s->vram);
s->vbe_mapped = 1;
#endif
}
diff --git a/hw/vga_int.h b/hw/vga_int.h
index d2811bd..0ef9962 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -23,6 +23,7 @@
*/
#include <hw/hw.h>
+#include "memory.h"
#define MSR_COLOR_EMULATION 0x01
#define MSR_PAGE_SELECT 0x20
@@ -103,15 +104,15 @@ struct VGACommonState;
typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
+typedef struct VGAMemoryRegion {
+ MemoryRegion mem;
+ struct VGACommonState *s;
+} VGAMemoryRegion;
+
typedef struct VGACommonState {
uint8_t *vram_ptr;
- ram_addr_t vram_offset;
+ MemoryRegion vram;
uint32_t vram_size;
- uint32_t lfb_addr;
- uint32_t lfb_end;
- uint32_t map_addr;
- uint32_t map_end;
- uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
uint32_t latch;
uint8_t sr_index;
uint8_t sr[256];
@@ -134,7 +135,7 @@ typedef struct VGACommonState {
int dac_8bit;
uint8_t palette[768];
int32_t bank_offset;
- int vga_io_memory;
+ VGAMemoryRegion *vga_io_memory;
int (*get_bpp)(struct VGACommonState *s);
void (*get_offsets)(struct VGACommonState *s,
uint32_t *pline_offset,
@@ -191,7 +192,7 @@ static inline int c6_to_8(int v)
void vga_common_init(VGACommonState *s, int vga_ram_size);
void vga_init(VGACommonState *s);
-int vga_init_io(VGACommonState *s);
+VGAMemoryRegion *vga_init_io(VGACommonState *s);
void vga_common_reset(VGACommonState *s);
void vga_dirty_log_start(VGACommonState *s);
@@ -229,5 +230,4 @@ extern const uint8_t gr_mask[16];
#define VGABIOS_FILENAME "vgabios.bin"
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
-extern CPUReadMemoryFunc * const vga_mem_read[3];
-extern CPUWriteMemoryFunc * const vga_mem_write[3];
+extern MemoryRegionOps vga_mem_ops;
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 190b005..cd7c508 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1135,17 +1135,45 @@ static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
*(uint32_t *) (s->vram_ptr + addr) = value;
}
-static CPUReadMemoryFunc * const vmsvga_vram_read[] = {
- vmsvga_vram_readb,
- vmsvga_vram_readw,
- vmsvga_vram_readl,
-};
+typedef struct DirectMem DirectMem;
-static CPUWriteMemoryFunc * const vmsvga_vram_write[] = {
- vmsvga_vram_writeb,
- vmsvga_vram_writew,
- vmsvga_vram_writel,
+struct DirectMem {
+ MemoryRegion mr;
+ struct vmsvga_state_s *chip;
};
+
+static uint64_t vmsvga_vram_read(MemoryRegion *mr, target_phys_addr_t addr,
+ unsigned size)
+{
+ struct vmsvga_state_s *s = container_of(mr, DirectMem, iomem)->chip;
+
+ switch (size) {
+ case 1: return vmsvga_vram_readb(s, addr);
+ case 2: return vmsvga_vram_readw(s, addr);
+ case 4: return vmsvga_vram_readl(s, addr);
+ default: abort();
+ }
+}
+
+static void vmsvga_vram_read(MemoryRegion *mr, target_phys_addr_t addr,
+ unsigned size, uint64_t data)
+{
+ struct vmsvga_state_s *s = container_of(mr, DirectMem, iomem)->chip;
+
+ switch (size) {
+ case 1: return vmsvga_vram_writeb(s, addr, data);
+ case 2: return vmsvga_vram_writew(s, addr, data);
+ case 4: return vmsvga_vram_writel(s, addr, data);
+ default: abort();
+ }
+}
+
+static MemoryRegionOps vmsvga_vram_io_ops = {
+ .read = vmsvga_vram_read,
+ .write = vmsvga_vram_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+}
+
#endif
static int vmsvga_post_load(void *opaque, int version_id)
@@ -1241,27 +1269,6 @@ static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1, 4, vmsvga_bios_write, s);
}
-static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
- struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
- struct vmsvga_state_s *s = &d->chip;
- ram_addr_t iomemtype;
-
-#ifdef DIRECT_VRAM
- iomemtype = cpu_register_io_memory(vmsvga_vram_read,
- vmsvga_vram_write, s, DEVICE_NATIVE_ENDIAN);
-#else
- iomemtype = s->vga.vram_offset | IO_MEM_RAM;
-#endif
- cpu_register_physical_memory(addr, s->vga.vram_size,
- iomemtype);
-
- s->vga.map_addr = addr;
- s->vga.map_end = addr + s->vga.vram_size;
- vga_dirty_log_restart(&s->vga);
-}
-
static void pci_vmsvga_map_fifo(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{
@@ -1279,6 +1286,20 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
{
struct pci_vmsvga_state_s *s =
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
+ MemoryRegion *iomem;
+
+#ifdef DIRECT_VRAM
+ DirectMem *directmem = qemu_malloc(sizeof(*directmem));
+
+ directmem->chip = &s->chip;
+ iomem = &directmem->mr;
+ memory_region_init_io(iomem, &vmsvga_vram_io_ops, "vmsvga",
+ memory_region_size(&s->chip.vga.vram));
+#else
+ iomem = &s->chip.vga.vram;
+#endif
+
+ vga_dirty_log_restart(&s->chip.vga);
s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
@@ -1286,8 +1307,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
pci_register_bar(&s->card, 0, 0x10,
PCI_BASE_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
- pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
- PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_mem);
+ pci_register_bar_region(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
pci_register_bar(&s->card, 2, SVGA_FIFO_SIZE,
PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_fifo);
--
1.7.5.3
--
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