On 05/18/2011 03:35 PM, Peter Zijlstra wrote:
On Wed, 2011-05-18 at 14:37 +0300, Avi Kivity wrote: > On 05/18/2011 02:32 PM, Peter Zijlstra wrote: > > On Wed, 2011-05-18 at 13:07 +0200, Ingo Molnar wrote: > > > > > > It does through raw events - which are indeed model specific. > > > > Which is exactly what is needed anyway, he gets a raw msr value. > > > > The only thing that is not exposed is the ANY bit, but since KVM doesn't > > expose HT anyway that doesn't matter. > > If I were to use raw events, I'd need to program AMD and Intel hosts > separately. As it is, I just use the generic counters and the perf > backend does its thing. But why exactly, from what I understood you emulate an actual hardware PMU, that means the guest will be writing proper content to the relevant MSRs, you can feed that directly into the raw config field (with exception of the USR/OS/INT bits).
I am emulating an architectural PMU on a machine that may not have one (Intel P4 or AMD), so I need translation between the different config formats and event codes.
I'm fairly sure that emulating the intel arch bits on an cpu that otherwise identifies itself as AMD is going to confuse things.
First, we can cheat and identify as Intel. Second, I'd like to change architectural PMU probing to ignore the vendor (pending confirmation from AMD that they won't implement cpuid leaf 0xa in a way that is incompatible with Intel). That's what architectural means, no?
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