On 12/07/2010 12:59 PM, Andre Przywara wrote:
Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara<andre.przywara@xxxxxxx> --- arch/x86/include/asm/svm.h | 2 + arch/x86/kvm/svm.c | 74 +++++++++++++++++++++++++++++++++++++++----- 2 files changed, 68 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 11dbca7..589fc25 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -256,6 +256,8 @@ struct __attribute__ ((__packed__)) vmcb { #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 +#define SVM_EXITINFO_REG_MASK 0x0F + #define SVM_EXIT_READ_CR0 0x000 #define SVM_EXIT_READ_CR3 0x003 #define SVM_EXIT_READ_CR4 0x004 diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index c573e2d..b7233fd 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -2594,12 +2594,70 @@ static int emulate_on_interception(struct vcpu_svm *svm) return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; } +static int cr_interception(struct vcpu_svm *svm) +{ + int reg, cr; + unsigned long val; + + if (!boot_cpu_has(SVM_FEATURE_DECODE_ASSIST) || + (svm->vmcb->control.exit_info_1& (1ULL<< 63)) == 0) + return emulate_on_interception(svm); + + reg = svm->vmcb->control.exit_info_1& SVM_EXITINFO_REG_MASK; + cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; + if (cr> 15) { /* mov to cr */ + val = kvm_register_read(&svm->vcpu, reg); + switch (cr& 0x0F) { + case 0: + kvm_set_cr0(&svm->vcpu, val); + break; + case 3: + kvm_set_cr3(&svm->vcpu, val); + break; + case 4: + kvm_set_cr4(&svm->vcpu, val); + break; + case 8: + kvm_set_cr8(&svm->vcpu, val& 0xfUL); + break; + default: + WARN(1, "unhandled write to CR%d", cr& 0x0F); + return EMULATE_FAIL; + }
...
+ } + skip_emulated_instruction(&svm->vcpu); + + return 1; +} +
Must not skip_emulated_instruction() if we inject an exception; see how vmx does this (handle_cr).
@@ -2864,14 +2922,14 @@ static int pause_interception(struct vcpu_svm *svm) } static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { - [SVM_EXIT_READ_CR0] = emulate_on_interception, - [SVM_EXIT_READ_CR3] = emulate_on_interception, - [SVM_EXIT_READ_CR4] = emulate_on_interception, - [SVM_EXIT_READ_CR8] = emulate_on_interception, + [SVM_EXIT_READ_CR0] = cr_interception, + [SVM_EXIT_READ_CR3] = cr_interception, + [SVM_EXIT_READ_CR4] = cr_interception, + [SVM_EXIT_READ_CR8] = cr_interception, [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, [SVM_EXIT_WRITE_CR0] = cr0_write_interception, - [SVM_EXIT_WRITE_CR3] = emulate_on_interception, - [SVM_EXIT_WRITE_CR4] = emulate_on_interception, + [SVM_EXIT_WRITE_CR3] = cr_interception, + [SVM_EXIT_WRITE_CR4] = cr_interception, [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
We could move cr[08]_write_interception into cr_interception, but that takes a bit more thought. Best done later.
[SVM_EXIT_READ_DR0] = emulate_on_interception, [SVM_EXIT_READ_DR1] = emulate_on_interception,
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