On 3/10/25 01:43, Nikunj A Dadhania wrote: > The Secure TSC feature for SEV-SNP allows guests to securely use the RDTSC > and RDTSCP instructions, ensuring that the parameters used cannot be > altered by the hypervisor once the guest is launched. For more details, > refer to the AMD64 APM Vol 2, Section "Secure TSC". > > Signed-off-by: Nikunj A Dadhania <nikunj@xxxxxxx> > Acked-by: Borislav Petkov (AMD) <bp@xxxxxxxxx> Reviewed-by: Tom Lendacky <thomas.lendacky@xxxxxxx> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 8f8aaf94dc00..68a4d6b4cc11 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -449,6 +449,7 @@ > #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* VM Page Flush MSR is supported */ > #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */ > #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */ > +#define X86_FEATURE_SNP_SECURE_TSC (19*32+ 8) /* SEV-SNP Secure TSC */ > #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ > #define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */ > #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
