Re: [PATCH v5 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

["Moger, Babu" <bmoger@xxxxxxx>]

Hi Zhao,

On 2/20/2025 5:26 AM, Zhao Liu wrote:
> > +static const CPUCaches epyc_milan_v3_cache_info = {
> > +    .l1d_cache = &(CPUCacheInfo) {
> > +        .type = DATA_CACHE,
> > +        .level = 1,
> > +        .size = 32 * KiB,
> > +        .line_size = 64,
> > +        .associativity = 8,
> > +        .partitions = 1,
> > +        .sets = 64,
> > +        .lines_per_tag = 1,
> > +        .self_init = 1,
>
> true.

Sure.

> > +        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> > +    },
> > +    .l1i_cache = &(CPUCacheInfo) {
> > +        .type = INSTRUCTION_CACHE,
> > +        .level = 1,
> > +        .size = 32 * KiB,
> > +        .line_size = 64,
> > +        .associativity = 8,
> > +        .partitions = 1,
> > +        .sets = 64,
> > +        .lines_per_tag = 1,
> > +        .self_init = 1,
>
> true.

Sure.

> Reviewed-by: Zhao Liu <zhao1.liu@xxxxxxxxx>

Thanks
Babu