On Mon, Feb 10, 2025 at 06:41:33PM +0000, Marc Zyngier wrote: > Provide the architected EC and ISS values for all the FEAT_LS64* > instructions. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > --- > arch/arm64/include/asm/esr.h | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > index d1b1a33f9a8b0..d5c2fac21a16c 100644 > --- a/arch/arm64/include/asm/esr.h > +++ b/arch/arm64/include/asm/esr.h > @@ -20,7 +20,8 @@ > #define ESR_ELx_EC_FP_ASIMD UL(0x07) > #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ > #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ > -/* Unallocated EC: 0x0A - 0x0B */ > +#define ESR_ELx_EC_LS64B UL(0x0A) This EC code has been generalised recently. In the latest ARM ARM (ARM DDI 0487 L.a), which can be found at: https://developer.arm.com/documentation/ddi0487/la/?lang=en ... the table on page D24-7333 refers to it as: | Trapped execution of any instruction not covered by other EC values. ... and the corresponding ISS description is named: | ISS encoding for an exception from any other instruction ... so maybe it makes sense to call it 'ESR_ELx_EC_OTHER_INSN', 'ESR_ELx_EC_INSN_MISC', or something of that rough shape? With that, the PSB CSYNC oddity in patch 15 makes a bit more sense, though the L.a release of the ARM ARM is still missing the description of that. Mark. > +/* Unallocated EC: 0x0B */ > #define ESR_ELx_EC_CP14_64 UL(0x0C) > #define ESR_ELx_EC_BTI UL(0x0D) > #define ESR_ELx_EC_ILL UL(0x0E) > @@ -174,6 +175,11 @@ > #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) > #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) > > +/* ISS definitions for LD64B/ST64B instructions */ > +#define ESR_ELx_ISS_ST64BV (0) > +#define ESR_ELx_ISS_ST64BV0 (1) > +#define ESR_ELx_ISS_LDST64B (2) > + > #define DISR_EL1_IDS (UL(1) << 24) > /* > * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean > -- > 2.39.2 >
