On 1/4/2025 6:04 AM, Vishal Annapurve wrote:
On Sun, Dec 8, 2024 at 5:12 PM Binbin Wu <binbin.wu@xxxxxxxxxxxxxxx> wrote:From: Isaku Yamahata <isaku.yamahata@xxxxxxxxx> ... +} + static void vt_apicv_pre_state_restore(struct kvm_vcpu *vcpu) { struct pi_desc *pi = vcpu_to_pi_desc(vcpu); @@ -236,6 +245,22 @@ static void vt_apicv_pre_state_restore(struct kvm_vcpu *vcpu) memset(pi->pir, 0, sizeof(pi->pir));Should this be a nop for TDX VMs? pre_state_restore could cause pending PIRs to get cleared as KVM doesn't have ability to sync them to vIRR in absence of access to the VAPIC page.
This callback is called by kvm_lapic_reset() and kvm_apic_set_state(). If it is call by kvm_lapic_reset(), it should be cleared. If it is called by kvm_apic_set_state() when userspace want to setup the lapic. It will be needed when live migration is enabled for TDX. For VMX VM, the PIR is synced to vIRR and then the state will be sent to destination VM. For TDX guest, I am not sure the final solution to sync PIR from source to destination TDX guest. I guess TDX module probably will do the job. Will ask Intel guys to check what is the solution. For this base series, TDX live migration is not supported yet, it is OK to reset PIR for now.
} +static void vt_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) +{ + if (is_td_vcpu(vcpu)) + return; + + return vmx_hwapic_irr_update(vcpu, max_irr); +} +
