On 12/19/24 09:32, Zhao Liu wrote:
Hi folks, This is my v6. since Phili has already merged the general smp cache part, v6 just includes the remaining i386-specific changes to support SMP cache topology for PC machine (currently all patches have got Reviewed-by from previous review). Compared with v5 [1], there's no change and just series just picks the unmerged patches and rebases on the master branch (based on the commit 8032c78e556c "Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu into staging"). The patch 4 ("i386/cpu: add has_caches flag to check smp_cache"), which introduced a has_caches flag, is also ARM side wanted. Though now this series targets to i386, to help review, I still include the previous introduction about smp cache topology feature. Background ========== The x86 and ARM (RISCV) need to allow user to configure cache properties (current only topology): * For x86, the default cache topology model (of max/host CPU) does not always match the Host's real physical cache topology. Performance can increase when the configured virtual topology is closer to the physical topology than a default topology would be. * For ARM, QEMU can't get the cache topology information from the CPU registers, then user configuration is necessary. Additionally, the cache information is also needed for MPAM emulation (for TCG) to build the right PPTT. (Originally from Jonathan) About smp-cache =============== The API design has been discussed heavily in [3]. Now, smp-cache is implemented as a array integrated in -machine. Though -machine currently can't support JSON format, this is the one of the directions of future. An example is as follows: smp_cache=smp-cache.0.cache=l1i,smp-cache.0.topology=core,smp-cache.1.cache=l1d,smp-cache.1.topology=core,smp-cache.2.cache=l2,smp-cache.2.topology=module,smp-cache.3.cache=l3,smp-cache.3.topology=die "cache" specifies the cache that the properties will be applied on. This field is the combination of cache level and cache type. Now it supports "l1d" (L1 data cache), "l1i" (L1 instruction cache), "l2" (L2 unified cache) and "l3" (L3 unified cache). "topology" field accepts CPU topology levels including "thread", "core", "module", "cluster", "die", "socket", "book", "drawer" and a special value "default".
Looks good; just one thing, does "thread" make sense? I think that it's almost by definition that threads within a core share all caches, but maybe I'm missing some hardware configurations.
Paolo
The "default" is introduced to make it easier for libvirt to set a default parameter value without having to care about the specific machine (because currently there is no proper way for machine to expose supported topology levels and caches). If "default" is set, then the cache topology will follow the architecture's default cache topology model. If other CPU topology level is set, the cache will be shared at corresponding CPU topology level. [1]: Patch v5: https://lore.kernel.org/qemu-devel/20241101083331.340178-1-zhao1.liu@xxxxxxxxx/ [2]: ARM smp-cache: https://lore.kernel.org/qemu-devel/20241010111822.345-1-alireza.sanaee@xxxxxxxxxx/ [3]: API disscussion: https://lore.kernel.org/qemu-devel/8734ndj33j.fsf@xxxxxxxxxxxx/ Thanks and Best Regards, Zhao --- Alireza Sanaee (1): i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu (3): i386/cpu: Support thread and module level cache topology i386/cpu: Update cache topology with machine's configuration i386/pc: Support cache topology in -machine for PC machine hw/core/machine-smp.c | 2 ++ hw/i386/pc.c | 4 +++ include/hw/boards.h | 3 ++ qemu-options.hx | 31 +++++++++++++++++- target/i386/cpu.c | 76 ++++++++++++++++++++++++++++++++++++++++--- 5 files changed, 111 insertions(+), 5 deletions(-)
