Re: [PATCH v5 08/12] iommufd: Enforce pasid compatible domain for PASID-capable device

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On 2024/12/11 16:46, Tian, Kevin wrote:
From: Liu, Yi L <yi.l.liu@xxxxxxxxx>
Sent: Tuesday, December 10, 2024 11:15 AM

On 2024/12/9 22:57, Jason Gunthorpe wrote:

I'm not sure, I think we should not make it dependent on the device
capability. There may be multiple devices in the iommufd and some of
them may be PASID capable. The PASID capable domains should interwork
with all of the devices. Thus I'd also expect to be able to allocate a
PASID capable domain on a non-pasid capable device. Even though that
would be pointless on its own.

yes. I also had an offline email to confirm with Vasant, and he confirmed
a non-pasid capable device should be able to use pasid-capable domain (V2
page table.

It's hard to think any vendor would want to that type of restriction.
whatever format adopted is purely IOMMU internal thing.


We want some reasonable compromise to encourage applications to use
IOMMU_HWPT_ALLOC_PASID properly, but not build too much complexity
to
reject driver-specific behavior.

I'm ok to do it in iommufd as long as it is only applicable to hwpt_paging.
Otherwise, attaching nested domain to pasid would be failed according to
the aforementioned enforcement.


IMHO we may want to have a general enforcement in IOMMUFD that
any domain (paging or nested) must have ALLOC_PASID set to be
used in pasid-oriented operations.

drivers can have more restrictions, e.g. for arm/amd allocating a nested
domain with that bit set will fail at the beginning.

ARM/AMD should allow allocating nested domain with this flag. Otherwise,
it does not suit the ALLOC_PASID definition. It requires both the PASID
path and non-PASID path to use pasid-compat domain.

So maybe we should not stick with the initial purpose of ALLOC_PASID flag.
It actually means selecting V2 page table. But the definition of it allows
us to consider the nested domains to be pasid-compat as Intel allows it.
And, a sane userspace running on ARM/AMD will never attach nested domain
to PASIDs. Even it does, the ARM SMMU and AMD iommu driver can fail such
attempts. In this way, we can enforce the ALLOC_PASID flag for any domains
used by PASID-capable devices in iommufd. This suits the existing
ALLOC_PASID definition as well.

@Jason, your opinion? With this open closed, I can update this series.

Regards,
Yi Liu




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