Hello:
This patch was applied to riscv/linux.git (fixes)
by Anup Patel <anup@xxxxxxxxxxxxxx>:
On Tue, 29 Oct 2024 16:55:39 +0800 you wrote:
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> "If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The pending bit is cleared whenever the rectified input value is
> low, when the interrupt is forwarded by MSI, or by a relevant
> write to an in_clrip register or to clripnum."
>
> [...]
Here is the summary with links:
- [v2,1/1] RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation
https://git.kernel.org/riscv/c/60821fb4dd73
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
