On Tue, Dec 03, 2024 at 02:30:39PM +0530, Nikunj A Dadhania wrote:
> diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c
> index 774f9677458f..fa0bc52ef707 100644
> --- a/arch/x86/mm/mem_encrypt_amd.c
> +++ b/arch/x86/mm/mem_encrypt_amd.c
> @@ -541,6 +541,10 @@ void __init sme_early_init(void)
> * kernel mapped.
> */
> snp_update_svsm_ca();
> +
> + /* Mark the TSC as reliable when Secure TSC is enabled */
> + if (sev_status & MSR_AMD64_SNP_SECURE_TSC)
> + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
What happens if someone writes MSR 0x10 on some CPU and thus makes the TSCs on
the host unsynchronized and that CPU runs a SecureTSC guest?
That guest would use RDTSC and get wrong values and turn the guest into
a mess, right?
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
