On 12/10/24 9:18 AM, Jason Gunthorpe wrote:
On Tue, Dec 10, 2024 at 02:07:40PM +0000, Will Deacon wrote:
On Mon, Nov 18, 2024 at 01:19:57PM +0000, ankita@xxxxxxxxxx wrote:
The changes are heavily influenced by the insightful discussions between
Catalin Marinas and Jason Gunthorpe [1] on v1. Many thanks for their
valuable suggestions.
Link: https://lore.kernel.org/lkml/20230907181459.18145-2-ankita@xxxxxxxxxx [1]
That's a different series, no? It got merged at v9:
I was confused by this too. v1 of that series included this patch, as
that series went along it became focused only on enabling WC
(Normal-NC) in a VM for device MMIO and this patch for device cachable
memory was dropped off.
There are two related things:
1) Device MMIO memory should be able to be Normal-NC in a VM. Already
merged
2) Device Cachable memory (ie CXL and pre-CXL coherently attached
memory) should be Normal Cachable in a VM, even if it doesn't have
struct page/etc. (this patch)
IIRC this part was dropped off because of the MTE complexity that
Catalin raised.
Jason
Jason & Catalin: Thanks for the filler for the splitting.
So, I'm not sure I read what is needed to resolve this patch.
I read Will's reply to split it further and basically along what logical lines of functionality;
is there still an MTE complexity that has to be resolved/included in the series?
IOW, I'm looking for a complete, clear (set of) statement(s) that Ankit can implement to get this (requested) series moving forward, sooner than later;
it's already been a year+ to get to this point, and I don't want further ambiguity/uncertainty to drag it out more than needed.
Thanks... Don
