On 12/6/24 21:11, Moger, Babu wrote:
On 12/4/2024 10:57 AM, Jim Mattson wrote:
On Wed, Dec 4, 2024 at 5:43 AM Maksim Davydov
<davydov-max@xxxxxxxxxxxxxx> wrote:
Fast short REP STOSB and fast short CMPSB support on AMD processors are
provided in other CPUID function in comparison with Intel processors:
* FSRS: 10 bit in 0x80000021_EAX
* FSRC: 11 bit in 0x80000021_EAX
I have to wonder why these bits aren't documented in the APM. I assume
you pulled them out of some PPR? I would be hesitant to include CPUID
bit definitions that may be microarchitecture-specific rather than
architectural.
Perhaps someone from AMD should at least ACK this change?
APM updates are in progress right now, but haven’t been able to get an ETA.
Will confirm once APM is released.
Thanks a lot!
It means that this series should be sent as 2 independent parts:
1. FSRS and FSRC will wait for updated APM
2. Speculation control bits will be sent as a separate patch
AMD bit numbers differ from existing definition of FSRC and
FSRS. So, the new appropriate values have to be added with new names.
It's safe to advertise these features to userspace because they are a part
of CPU model definition and they can't be disabled (as existing Intel
features).
Fixes: 2a4209d6a9cb ("KVM: x86: Advertise fast REP string features inherent to the CPU")
Signed-off-by: Maksim Davydov<davydov-max@xxxxxxxxxxxxxx>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kvm/cpuid.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 17b6590748c0..45f87a026bba 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -460,6 +460,8 @@
#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* Null Selector Clears Base */
#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* Automatic IBRS */
#define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* SMM_CTL MSR is not present */
+#define X86_FEATURE_AMD_FSRS (20*32+10) /* AMD Fast short REP STOSB supported */
+#define X86_FEATURE_AMD_FSRC (20*32+11) /* AMD Fast short REP CMPSB supported */
#define X86_FEATURE_SBPB (20*32+27) /* Selective Branch Prediction Barrier */
#define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 097bdc022d0f..7bc095add8ee 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -799,8 +799,8 @@ void kvm_set_cpu_caps(void)
kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
- F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
- F(WRMSR_XX_BASE_NS)
+ F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | F(AMD_FSRS) |
+ F(AMD_FSRC) | 0 /* PrefetchCtlMsr */ | F(WRMSR_XX_BASE_NS)
);
kvm_cpu_cap_check_and_set(X86_FEATURE_SBPB);
--
2.34.1
--
Best regards,
Maksim Davydov
