On Thu, Dec 05, 2024, Nathan Chancellor wrote:
> Hi Boris and x86 + KVM folks,
>
> I got access to a new box that has an EPYC 9454P in it and I noticed
> that I hit the warning from
>
> /*
> * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up
> * using the trampoline code and as part of it, MSR_EFER gets prepared there in
> * order to be replicated onto them. Regardless, set it here again, if not set,
> * to protect against any future refactoring/code reorganization which might
> * miss setting this important bit.
> */
> if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
> cpu_has(c, X86_FEATURE_AUTOIBRS))
> WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
>
> that was added by commit 8cc68c9c9e92 ("x86/CPU/AMD: Make sure
> EFER[AIBRSE] is set") when booting a 32-bit kernel in QEMU with KVM. I
> do not see this without KVM, so maybe this has something to do with
> commit 8c19b6f257fa ("KVM: x86: Propagate the AMD Automatic IBRS feature
> to the guest") as well?
This is a bug in the above code. msr_set_bit() returns '1' on a successful write.
Presumably spectre_v2_select_mitigation() sets EFER.AUTOIBRS when booting on bare
metal, in which case msr_set_bit() returns '0' because the bit is already set.
--
From: Sean Christopherson <seanjc@xxxxxxxxxx>
Date: Fri, 6 Dec 2024 08:14:45 -0800
Subject: [PATCH] x86/CPU/AMD: WARN when setting EFER.AUTOIBRS if and only if
the WRMSR fails
When ensuring EFER.AUTOIBRS is set, WARN only on a negative return code
from msr_set_bit(), as '1' is used to indicate the WRMSR was successful
('0' indicates the MSR bit was already set).
Fixes: 8cc68c9c9e92 ("x86/CPU/AMD: Make sure EFER[AIBRSE] is set")
Reported-by: Nathan Chancellor <nathan@xxxxxxxxxx>
Closes: https://lore.kernel.org/all/20241205220604.GA2054199@thelio-3990X
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
---
arch/x86/kernel/cpu/amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index d8408aafeed9..79d2e17f6582 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1065,7 +1065,7 @@ static void init_amd(struct cpuinfo_x86 *c)
*/
if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
cpu_has(c, X86_FEATURE_AUTOIBRS))
- WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
+ WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0);
/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
base-commit: b8f52214c61a5b99a54168145378e91b40d10c90
--
