On 11/7/2024 12:50 AM, Melody (Huibo) Wang wrote: > Hi Neeraj, > > On 9/13/2024 4:36 AM, Neeraj Upadhyay wrote: >> The x2APIC registers are mapped at an offset within the guest APIC >> backing page which is same as their x2APIC MMIO offset. Secure AVIC >> adds new registers such as ALLOWED_IRRs (which are at 4-byte offset >> within the IRR register offset range) and NMI_REQ to the APIC register >> space. In addition, the APIC_ID register is writable and configured by >> guest. >> >> Add read() and write() APIC callback functions to read and write x2APIC >> registers directly from the guest APIC backing page. >> >> The default .read()/.write() callbacks of x2APIC drivers perform >> a rdmsr/wrmsr of the x2APIC registers. When Secure AVIC is enabled, >> these would result in #VC exception (for non-accelerated register >> accesses). The #VC exception handler reads/write the x2APIC register >> in the guest APIC backing page. Since this would increase the latency >> of accessing x2APIC registers, the read() and write() callbacks of >> Secure AVIC driver directly reads/writes to the guest APIC backing page. >> > I think this is important non-obvious information which should be in a comment in the code > itself, not just in the commit message. > Sure, I will add some of this information in the comments. Thanks for the review! - Neeraj > Thanks, > Melody
