SM3 is a new set of instructions in the latest Intel platform Clearwater Forest, which contains VSM3MSG1, VSM3MSG2, VSM3RNDS2. SM3 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 1]. SM3 is on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Considering SM3 itself has no truly kernel usages, hide this one in /proc/cpuinfo. These instructions only operate in xmm registers and have no new VMX controls, so there is no additional host enabling required for guests to use these instructions, i.e. advertising SM3 CPUID to userspace is safe. Tested-by: Jiaan Lu <jiaan.lu@xxxxxxxxx> Tested-by: Xuelian Guo <xuelian.guo@xxxxxxxxx> Signed-off-by: Tao Su <tao1.su@xxxxxxxxxxxxxxx> --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 896794528b81..460f4f93b039 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -318,6 +318,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_SHA512 (12*32+ 0) /* SHA512 instructions */ +#define X86_FEATURE_SM3 (12*32+ 1) /* SM3 instructions */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 5c7772567a4e..e9f7489ba569 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -698,8 +698,8 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(SHA512) | F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | - F(FZRM) | F(FSRS) | F(FSRC) | + F(SHA512) | F(SM3) | F(AVX_VNNI) | F(AVX512_BF16) | + F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | F(AMX_FP16) | F(AVX_IFMA) | F(LAM) ); -- 2.34.1
