On 10/31/24 08:39, Amit Shah wrote: ... > With the Enhanced Return Address Prediction Security feature, any > hardware TLB flush results in flushing of the RSB (aka RAP in AMD spec). > This guarantees an RSB flush across context switches. Check out the APM, volume 2: "5.5.1 Process Context Identifier" ... when system software switches address spaces (by writing ... CR3[62:12]), the processor may use TLB mappings previously stored for that address space and PCID, providing that bit 63 of the source operand is set to 1. tl;dr: PCIDs mean you don't necessarily flush the TLB on context switches.
