tl;dr - these patches are improvement to the riscv framework to better support the SBI HSM tests. The first patch is a simpler alternative to [1] and [2] which doesn't require us to decide how best to make the number configurable. The second patch just adds sanity checking to make sure we can expect the SBI implementation to accept all hartids mapped from the present mask. The third patch was already posted once before[3] with a slightly different summary. It and the last patch improve smp_boot_secondary() since the SBI HSM tests were attempting to make workarounds for odd behaviors. [1] https://lore.kernel.org/all/20240820170150.377580-2-andrew.jones@xxxxxxxxx/ [2] https://lore.kernel.org/all/20240903143946.834864-6-andrew.jones@xxxxxxxxx/ [3] https://lore.kernel.org/all/20240904120812.1798715-2-andrew.jones@xxxxxxxxx/ Andrew Jones (4): riscv: Bump NR_CPUS to 256 riscv: Filter unmanaged harts from present mask riscv: Fix secondary_entry riscv: Rework smp_boot_secondary lib/riscv/asm/processor.h | 1 + lib/riscv/asm/setup.h | 2 +- lib/riscv/setup.c | 11 ++++++--- lib/riscv/smp.c | 49 +++++++++++++++++++++++++++------------ riscv/cstart.S | 7 +++--- 5 files changed, 48 insertions(+), 22 deletions(-) -- 2.47.0
