In SNP guest environment with Secure TSC enabled, unlike other clock sources (such as HPET, ACPI timer, APIC, etc.), the RDTSC instruction is handled without causing a VM exit, resulting in minimal overhead and jitters. Hence, mark Secure TSC as the only reliable clock source, bypassing unstable calibration. Signed-off-by: Nikunj A Dadhania <nikunj@xxxxxxx> Tested-by: Peter Gonda <pgonda@xxxxxxxxxx> Reviewed-by: Tom Lendacky <thomas.lendacky@xxxxxxx> --- arch/x86/mm/mem_encrypt_amd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index 86a476a426c2..e9fb5f24703a 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -516,6 +516,10 @@ void __init sme_early_init(void) * kernel mapped. */ snp_update_svsm_ca(); + + /* Mark the TSC as reliable when Secure TSC is enabled */ + if (sev_status & MSR_AMD64_SNP_SECURE_TSC) + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); } void __init mem_encrypt_free_decrypted_mem(void) -- 2.34.1
